
David J. Goodwin
Examiner (ID: 9508, Phone: (571)272-8451 , Office: P/2817 )
| Most Active Art Unit | 2817 |
| Art Unit(s) | 2818, 2817, 2822 |
| Total Applications | 1087 |
| Issued Applications | 703 |
| Pending Applications | 110 |
| Abandoned Applications | 299 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 18424237
[patent_doc_number] => 20230178701
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-06-08
[patent_title] => ELECTRONIC DEVICE
[patent_app_type] => utility
[patent_app_number] => 18/051543
[patent_app_country] => US
[patent_app_date] => 2022-11-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5801
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -19
[patent_words_short_claim] => 100
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18051543
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/051543 | ELECTRONIC DEVICE | Oct 31, 2022 | Pending |
Array
(
[id] => 19143621
[patent_doc_number] => 20240142496
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-05-02
[patent_title] => CONDUCTIVE PERFORATED PLATE FOR ELECTRICAL TEST
[patent_app_type] => utility
[patent_app_number] => 17/975071
[patent_app_country] => US
[patent_app_date] => 2022-10-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 11202
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 57
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17975071
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/975071 | CONDUCTIVE PERFORATED PLATE FOR ELECTRICAL TEST | Oct 26, 2022 | Pending |
Array
(
[id] => 18774310
[patent_doc_number] => 20230369141
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-11-16
[patent_title] => SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
[patent_app_type] => utility
[patent_app_number] => 17/974205
[patent_app_country] => US
[patent_app_date] => 2022-10-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10473
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -21
[patent_words_short_claim] => 63
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17974205
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/974205 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME | Oct 25, 2022 | Pending |
Array
(
[id] => 19086254
[patent_doc_number] => 20240113055
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-04-04
[patent_title] => STRUCTURE FOR HYBRID BOND CRACKSTOP WITH AIRGAPS
[patent_app_type] => utility
[patent_app_number] => 17/937429
[patent_app_country] => US
[patent_app_date] => 2022-09-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5346
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 60
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17937429
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/937429 | STRUCTURE FOR HYBRID BOND CRACKSTOP WITH AIRGAPS | Sep 29, 2022 | Pending |
Array
(
[id] => 18162036
[patent_doc_number] => 20230028628
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-01-26
[patent_title] => PACKAGE STRUCTURE, PACKAGING METHOD AND SEMICONDUCTOR DEVICE
[patent_app_type] => utility
[patent_app_number] => 17/955681
[patent_app_country] => US
[patent_app_date] => 2022-09-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8020
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -10
[patent_words_short_claim] => 175
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17955681
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/955681 | PACKAGE STRUCTURE, PACKAGING METHOD AND SEMICONDUCTOR DEVICE | Sep 28, 2022 | Pending |
Array
(
[id] => 19071100
[patent_doc_number] => 20240105526
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-03-28
[patent_title] => ELECTRONIC DEVICE, ELECTRONIC STRUCTURE AND METHOD OF MANUFACTURING THE SAME
[patent_app_type] => utility
[patent_app_number] => 17/954752
[patent_app_country] => US
[patent_app_date] => 2022-09-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 11063
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 75
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17954752
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/954752 | ELECTRONIC DEVICE, ELECTRONIC STRUCTURE AND METHOD OF MANUFACTURING THE SAME | Sep 27, 2022 | Pending |
Array
(
[id] => 18147150
[patent_doc_number] => 20230021007
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-01-19
[patent_title] => TEST STRUCTURE AND METHOD FOR FORMING THE SAME, AND SEMICONDUCTOR MEMORY
[patent_app_type] => utility
[patent_app_number] => 17/935572
[patent_app_country] => US
[patent_app_date] => 2022-09-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6067
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -13
[patent_words_short_claim] => 120
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17935572
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/935572 | TEST STRUCTURE AND METHOD FOR FORMING THE SAME, AND SEMICONDUCTOR MEMORY | Sep 25, 2022 | Pending |
Array
(
[id] => 19054749
[patent_doc_number] => 20240096718
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-03-21
[patent_title] => TESTKEY STRUCTURE AND METHOD FOR FORMING THE SAME
[patent_app_type] => utility
[patent_app_number] => 17/945606
[patent_app_country] => US
[patent_app_date] => 2022-09-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 3876
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 106
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17945606
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/945606 | TESTKEY STRUCTURE AND METHOD FOR FORMING THE SAME | Sep 14, 2022 | Pending |
Array
(
[id] => 18139584
[patent_doc_number] => 20230013420
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-01-19
[patent_title] => SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD THEREOF
[patent_app_type] => utility
[patent_app_number] => 17/945109
[patent_app_country] => US
[patent_app_date] => 2022-09-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9500
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -13
[patent_words_short_claim] => 131
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17945109
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/945109 | SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD THEREOF | Sep 14, 2022 | Pending |
Array
(
[id] => 19038217
[patent_doc_number] => 20240088032
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-03-14
[patent_title] => Structure and Method of Fabrication for High Performance Integrated Passive Device
[patent_app_type] => utility
[patent_app_number] => 17/932182
[patent_app_country] => US
[patent_app_date] => 2022-09-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 3559
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -19
[patent_words_short_claim] => 27
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17932182
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/932182 | Structure and Method of Fabrication for High Performance Integrated Passive Device | Sep 13, 2022 | Pending |
Array
(
[id] => 19670851
[patent_doc_number] => 12183621
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-12-31
[patent_title] => Methods for adjusting surface topography of a substrate support apparatus
[patent_app_type] => utility
[patent_app_number] => 17/931444
[patent_app_country] => US
[patent_app_date] => 2022-09-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 23
[patent_no_of_words] => 8194
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 156
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17931444
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/931444 | Methods for adjusting surface topography of a substrate support apparatus | Sep 11, 2022 | Issued |
Array
(
[id] => 19038269
[patent_doc_number] => 20240088084
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-03-14
[patent_title] => TIGHTLY-COUPLED RANDOM ACCESS MEMORY INTERFACE SHIM DIE
[patent_app_type] => utility
[patent_app_number] => 17/943104
[patent_app_country] => US
[patent_app_date] => 2022-09-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6380
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 86
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17943104
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/943104 | TIGHTLY-COUPLED RANDOM ACCESS MEMORY INTERFACE SHIM DIE | Sep 11, 2022 | Pending |
Array
(
[id] => 18655260
[patent_doc_number] => 20230301111
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-09-21
[patent_title] => SEMICONDUCTOR STORAGE DEVICE AND METHOD OF MANUFACTURING THE SAME
[patent_app_type] => utility
[patent_app_number] => 17/941987
[patent_app_country] => US
[patent_app_date] => 2022-09-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10426
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 156
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17941987
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/941987 | SEMICONDUCTOR STORAGE DEVICE AND METHOD OF MANUFACTURING THE SAME | Sep 8, 2022 | Pending |
Array
(
[id] => 18210219
[patent_doc_number] => 20230056480
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-02-23
[patent_title] => Electroluminescent Display Device
[patent_app_type] => utility
[patent_app_number] => 17/886894
[patent_app_country] => US
[patent_app_date] => 2022-08-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 12857
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 110
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17886894
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/886894 | Electroluminescent Display Device | Aug 11, 2022 | Pending |
Array
(
[id] => 18196164
[patent_doc_number] => 20230049683
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-02-16
[patent_title] => FORMATION OF MEMORY DIE AND LOGIC DIE WITH WAFER-ON-WAFER BOND
[patent_app_type] => utility
[patent_app_number] => 17/884775
[patent_app_country] => US
[patent_app_date] => 2022-08-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 11442
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -20
[patent_words_short_claim] => 72
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17884775
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/884775 | FORMATION OF MEMORY DIE AND LOGIC DIE WITH WAFER-ON-WAFER BOND | Aug 9, 2022 | Pending |
Array
(
[id] => 18243927
[patent_doc_number] => 20230076238
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-03-09
[patent_title] => SEMICONDUCTOR CHIP WITH STEPPED SIDEWALL, SEMICONDUCTOR PACKAGE INCLUDING THE SAME, AND METHOD OF FABRICATING THE SAME
[patent_app_type] => utility
[patent_app_number] => 17/882748
[patent_app_country] => US
[patent_app_date] => 2022-08-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10044
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17882748
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/882748 | SEMICONDUCTOR CHIP WITH STEPPED SIDEWALL, SEMICONDUCTOR PACKAGE INCLUDING THE SAME, AND METHOD OF FABRICATING THE SAME | Aug 7, 2022 | Pending |
Array
(
[id] => 18040199
[patent_doc_number] => 20220384416
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-12-01
[patent_title] => DUMMY POLY LAYOUT FOR HIGH DENSITY DEVICES
[patent_app_type] => utility
[patent_app_number] => 17/881960
[patent_app_country] => US
[patent_app_date] => 2022-08-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7711
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 162
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17881960
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/881960 | Dummy poly layout for high density devices | Aug 4, 2022 | Issued |
Array
(
[id] => 18024254
[patent_doc_number] => 20220375753
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-11-24
[patent_title] => Doping Techniques
[patent_app_type] => utility
[patent_app_number] => 17/882177
[patent_app_country] => US
[patent_app_date] => 2022-08-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 3765
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -13
[patent_words_short_claim] => 55
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17882177
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/882177 | Doping techniques | Aug 4, 2022 | Issued |
Array
(
[id] => 20416833
[patent_doc_number] => 12500127
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-12-16
[patent_title] => Method of fabricating semiconductor structure
[patent_app_type] => utility
[patent_app_number] => 17/873182
[patent_app_country] => US
[patent_app_date] => 2022-07-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 28
[patent_figures_cnt] => 28
[patent_no_of_words] => 3023
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 100
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17873182
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/873182 | Method of fabricating semiconductor structure | Jul 25, 2022 | Issued |
Array
(
[id] => 18040116
[patent_doc_number] => 20220384333
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-12-01
[patent_title] => Sensor Package and Method
[patent_app_type] => utility
[patent_app_number] => 17/814995
[patent_app_country] => US
[patent_app_date] => 2022-07-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10788
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 95
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17814995
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/814995 | Sensor Package and Method | Jul 25, 2022 | Pending |