Search

David J. Goodwin

Examiner (ID: 4085, Phone: (571)272-8451 , Office: P/2817 )

Most Active Art Unit
2817
Art Unit(s)
2818, 2822, 2817
Total Applications
1103
Issued Applications
710
Pending Applications
110
Abandoned Applications
301

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17993471 [patent_doc_number] => 20220359508 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-10 [patent_title] => INTEGRATED CIRCUIT HAVING FINS CROSSING CELL BOUNDARY [patent_app_type] => utility [patent_app_number] => 17/871239 [patent_app_country] => US [patent_app_date] => 2022-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12918 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17871239 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/871239
Integrated circuit having fins crossing cell boundary Jul 21, 2022 Issued
Array ( [id] => 19765964 [patent_doc_number] => 12224265 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-02-11 [patent_title] => Three-dimensional stacking structure and manufacturing method thereof [patent_app_type] => utility [patent_app_number] => 17/855825 [patent_app_country] => US [patent_app_date] => 2022-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 18 [patent_no_of_words] => 7094 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17855825 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/855825
Three-dimensional stacking structure and manufacturing method thereof Jun 30, 2022 Issued
Array ( [id] => 20111588 [patent_doc_number] => 12362324 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-15 [patent_title] => Stack type semiconductor device and method of testing the stack type semiconductor device [patent_app_type] => utility [patent_app_number] => 17/851962 [patent_app_country] => US [patent_app_date] => 2022-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 13 [patent_no_of_words] => 6595 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 305 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17851962 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/851962
Stack type semiconductor device and method of testing the stack type semiconductor device Jun 27, 2022 Issued
Array ( [id] => 18352632 [patent_doc_number] => 20230140743 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-04 [patent_title] => SEALING RING, STACKED STRUCTURE, AND METHOD FOR MANUFACTURING SEALING RING [patent_app_type] => utility [patent_app_number] => 17/849963 [patent_app_country] => US [patent_app_date] => 2022-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5990 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17849963 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/849963
Sealing ring, stacked structure, and method for manufacturing sealing ring Jun 26, 2022 Issued
Array ( [id] => 17933608 [patent_doc_number] => 20220328734 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-13 [patent_title] => LIGHT-EMITTING DEVICE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/850549 [patent_app_country] => US [patent_app_date] => 2022-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5378 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17850549 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/850549
Light-emitting device and manufacturing method thereof Jun 26, 2022 Issued
Array ( [id] => 19951261 [patent_doc_number] => 12322632 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-06-03 [patent_title] => Substrate alignment systems and related methods [patent_app_type] => utility [patent_app_number] => 17/808716 [patent_app_country] => US [patent_app_date] => 2022-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 3 [patent_no_of_words] => 0 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17808716 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/808716
Substrate alignment systems and related methods Jun 23, 2022 Issued
Array ( [id] => 18081056 [patent_doc_number] => 20220406668 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-22 [patent_title] => ELECTRONIC CHIP [patent_app_type] => utility [patent_app_number] => 17/839976 [patent_app_country] => US [patent_app_date] => 2022-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5449 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17839976 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/839976
ELECTRONIC CHIP Jun 13, 2022 Pending
Array ( [id] => 18347308 [patent_doc_number] => 20230135418 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-04 [patent_title] => FUSE STRUCTURE, METHOD FOR MANUFACTURING SAME AND PROGRAMMABLE MEMORY [patent_app_type] => utility [patent_app_number] => 17/806251 [patent_app_country] => US [patent_app_date] => 2022-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4336 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17806251 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/806251
FUSE STRUCTURE, METHOD FOR MANUFACTURING SAME AND PROGRAMMABLE MEMORY Jun 8, 2022 Pending
Array ( [id] => 17870803 [patent_doc_number] => 20220293540 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-15 [patent_title] => SEMICONDUCTOR STRUCTURE AND METHOD OF FABRICATING THE SAME [patent_app_type] => utility [patent_app_number] => 17/827982 [patent_app_country] => US [patent_app_date] => 2022-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5941 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17827982 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/827982
SEMICONDUCTOR STRUCTURE AND METHOD OF FABRICATING THE SAME May 29, 2022 Pending
Array ( [id] => 18789314 [patent_doc_number] => 20230377967 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-23 [patent_title] => METHOD OF FORMING THROUGH SILICON VIA AND TRENCH USING THE SAME MASK LAYER [patent_app_type] => utility [patent_app_number] => 17/751297 [patent_app_country] => US [patent_app_date] => 2022-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3878 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17751297 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/751297
METHOD OF FORMING THROUGH SILICON VIA AND TRENCH USING THE SAME MASK LAYER May 22, 2022 Abandoned
Array ( [id] => 18144641 [patent_doc_number] => 20230018493 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-01-19 [patent_title] => Display Device [patent_app_type] => utility [patent_app_number] => 17/749806 [patent_app_country] => US [patent_app_date] => 2022-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8321 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 42 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17749806 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/749806
Display Device May 19, 2022 Pending
Array ( [id] => 18789545 [patent_doc_number] => 20230378230 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-23 [patent_title] => RECESSED BLOCKING STRUCTURE FOR BLC PIXELS [patent_app_type] => utility [patent_app_number] => 17/749390 [patent_app_country] => US [patent_app_date] => 2022-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7824 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17749390 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/749390
Recessed blocking structure for BLC pixels May 19, 2022 Issued
Array ( [id] => 20404445 [patent_doc_number] => 12494426 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-12-09 [patent_title] => Transistor capable of electrically controlling a threshold voltage and semiconductor device including the transistor [patent_app_type] => utility [patent_app_number] => 17/748291 [patent_app_country] => US [patent_app_date] => 2022-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 24 [patent_no_of_words] => 5269 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 203 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17748291 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/748291
Transistor capable of electrically controlling a threshold voltage and semiconductor device including the transistor May 18, 2022 Issued
Array ( [id] => 18821292 [patent_doc_number] => 20230395633 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-07 [patent_title] => IMAGE SENSOR PACKAGING STRUCTURES AND RELATED METHODS [patent_app_type] => utility [patent_app_number] => 17/664138 [patent_app_country] => US [patent_app_date] => 2022-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3598 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 41 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17664138 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/664138
IMAGE SENSOR PACKAGING STRUCTURES AND RELATED METHODS May 18, 2022 Abandoned
Array ( [id] => 19828846 [patent_doc_number] => 12249642 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-03-11 [patent_title] => Vertical insulated gate power switch with isolated base contact regions [patent_app_type] => utility [patent_app_number] => 17/747739 [patent_app_country] => US [patent_app_date] => 2022-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 16 [patent_no_of_words] => 3133 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 300 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17747739 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/747739
Vertical insulated gate power switch with isolated base contact regions May 17, 2022 Issued
Array ( [id] => 19610929 [patent_doc_number] => 12159810 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-12-03 [patent_title] => Semiconductor device [patent_app_type] => utility [patent_app_number] => 17/746492 [patent_app_country] => US [patent_app_date] => 2022-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 13 [patent_no_of_words] => 6559 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 279 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17746492 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/746492
Semiconductor device May 16, 2022 Issued
Array ( [id] => 18458914 [patent_doc_number] => 20230200196 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-22 [patent_title] => DEPOSITION DEVICE AND DEPOSITION METHOD [patent_app_type] => utility [patent_app_number] => 17/745365 [patent_app_country] => US [patent_app_date] => 2022-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7946 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17745365 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/745365
DEPOSITION DEVICE AND DEPOSITION METHOD May 15, 2022 Pending
Array ( [id] => 18776563 [patent_doc_number] => 20230371405 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-16 [patent_title] => PHASE CHANGE HETEROSTRUCTURES WITH CONTROLLED LINEAR DYNAMIC RANGE [patent_app_type] => utility [patent_app_number] => 17/663236 [patent_app_country] => US [patent_app_date] => 2022-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4066 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17663236 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/663236
PHASE CHANGE HETEROSTRUCTURES WITH CONTROLLED LINEAR DYNAMIC RANGE May 12, 2022 Pending
Array ( [id] => 19973916 [patent_doc_number] => 12342549 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-06-24 [patent_title] => Integrated circuitry, array of cross-point memory cells, method used in forming integrated circuitry [patent_app_type] => utility [patent_app_number] => 17/742154 [patent_app_country] => US [patent_app_date] => 2022-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 24 [patent_no_of_words] => 0 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 194 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17742154 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/742154
Integrated circuitry, array of cross-point memory cells, method used in forming integrated circuitry May 10, 2022 Issued
Array ( [id] => 19873841 [patent_doc_number] => 12266713 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-04-01 [patent_title] => Transistor with dielectric spacers and method of fabrication therefor [patent_app_type] => utility [patent_app_number] => 17/661827 [patent_app_country] => US [patent_app_date] => 2022-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 33 [patent_figures_cnt] => 33 [patent_no_of_words] => 13710 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17661827 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/661827
Transistor with dielectric spacers and method of fabrication therefor May 2, 2022 Issued
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