Search

David J. Huisman

Examiner (ID: 4847, Phone: (571)272-4168 , Office: P/2183 )

Most Active Art Unit
2183
Art Unit(s)
2183
Total Applications
930
Issued Applications
493
Pending Applications
141
Abandoned Applications
335

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19819027 [patent_doc_number] => 20250077234 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-06 [patent_title] => EXECUTION METHOD FOR INSTRUCTION CONFLICT, INSTRUCTION PROCESSING MODULE AND PROCESSOR [patent_app_type] => utility [patent_app_number] => 18/819125 [patent_app_country] => US [patent_app_date] => 2024-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5545 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18819125 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/819125
EXECUTION METHOD FOR INSTRUCTION CONFLICT, INSTRUCTION PROCESSING MODULE AND PROCESSOR Aug 28, 2024 Pending
Array ( [id] => 19695021 [patent_doc_number] => 20250013566 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-09 [patent_title] => ALLOCATION OF THREAD LOCAL STORAGE WHEN A THREAD SWITCHES BETWEEN LINK DOMAINS SHARING A COMMON ADDRESS SPACE [patent_app_type] => utility [patent_app_number] => 18/763532 [patent_app_country] => US [patent_app_date] => 2024-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5548 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18763532 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/763532
ALLOCATION OF THREAD LOCAL STORAGE WHEN A THREAD SWITCHES BETWEEN LINK DOMAINS SHARING A COMMON ADDRESS SPACE Jul 2, 2024 Pending
Array ( [id] => 19530203 [patent_doc_number] => 20240354105 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-24 [patent_title] => APPARATUS AND METHOD FOR PERFORMING A SPLICE OPERATION [patent_app_type] => utility [patent_app_number] => 18/762800 [patent_app_country] => US [patent_app_date] => 2024-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9375 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 311 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18762800 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/762800
APPARATUS AND METHOD FOR PERFORMING A SPLICE OPERATION Jul 2, 2024 Pending
Array ( [id] => 19588282 [patent_doc_number] => 20240385839 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-21 [patent_title] => PROCESSING METHOD OF MIXED PRECISION OPERATION AND INSTRUCTION PROCESSING APPARATUS [patent_app_type] => utility [patent_app_number] => 18/665108 [patent_app_country] => US [patent_app_date] => 2024-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8584 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18665108 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/665108
PROCESSING METHOD OF MIXED PRECISION OPERATION AND INSTRUCTION PROCESSING APPARATUS May 14, 2024 Pending
Array ( [id] => 19864765 [patent_doc_number] => 20250103551 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-27 [patent_title] => Interleave Execution Circuit [patent_app_type] => utility [patent_app_number] => 18/628460 [patent_app_country] => US [patent_app_date] => 2024-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 24872 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18628460 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/628460
Interleave Execution Circuit Apr 4, 2024 Pending
Array ( [id] => 20281704 [patent_doc_number] => 20250306946 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-10-02 [patent_title] => INDEPENDENT PROGRESS OF LANES IN A VECTOR PROCESSOR [patent_app_type] => utility [patent_app_number] => 18/618939 [patent_app_country] => US [patent_app_date] => 2024-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4741 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18618939 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/618939
INDEPENDENT PROGRESS OF LANES IN A VECTOR PROCESSOR Mar 26, 2024 Pending
Array ( [id] => 18957501 [patent_doc_number] => 20240045828 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-08 [patent_title] => COLLECTIVE COMMUNICATION METHOD AND SYSTEM, AND COMPUTER DEVICE [patent_app_type] => utility [patent_app_number] => 18/488454 [patent_app_country] => US [patent_app_date] => 2023-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13923 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18488454 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/488454
COLLECTIVE COMMUNICATION METHOD AND SYSTEM, AND COMPUTER DEVICE Oct 16, 2023 Pending
Array ( [id] => 19084853 [patent_doc_number] => 20240111654 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-04-04 [patent_title] => HYBRID PERFORMANCE MONITORING UNIT (PMU) ENUMERATION [patent_app_type] => utility [patent_app_number] => 18/374296 [patent_app_country] => US [patent_app_date] => 2023-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17509 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 47 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18374296 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/374296
HYBRID PERFORMANCE MONITORING UNIT (PMU) ENUMERATION Sep 27, 2023 Pending
Array ( [id] => 18881280 [patent_doc_number] => 20240004649 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-04 [patent_title] => METHOD AND APPARATUS FOR COMPRESSING VECTOR DATA, METHOD AND APPARATUS FOR DECOMPRESSING VECTOR DATA, AND DEVICE [patent_app_type] => utility [patent_app_number] => 18/368419 [patent_app_country] => US [patent_app_date] => 2023-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17455 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18368419 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/368419
METHOD AND APPARATUS FOR COMPRESSING VECTOR DATA, METHOD AND APPARATUS FOR DECOMPRESSING VECTOR DATA, AND DEVICE Sep 13, 2023 Pending
Array ( [id] => 19819292 [patent_doc_number] => 20250077499 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-06 [patent_title] => DATA STRUCTURE MARSHALLING UNIT [patent_app_type] => utility [patent_app_number] => 18/240632 [patent_app_country] => US [patent_app_date] => 2023-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 24685 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18240632 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/240632
DATA STRUCTURE MARSHALLING UNIT Aug 30, 2023 Pending
Array ( [id] => 18957353 [patent_doc_number] => 20240045680 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-08 [patent_title] => Coprocessor Register Renaming [patent_app_type] => utility [patent_app_number] => 18/453010 [patent_app_country] => US [patent_app_date] => 2023-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13431 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18453010 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/453010
Coprocessor Register Renaming Aug 20, 2023 Pending
Array ( [id] => 19573767 [patent_doc_number] => 20240378059 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-14 [patent_title] => Method for superscalar delay optimization [patent_app_type] => utility [patent_app_number] => 18/351765 [patent_app_country] => US [patent_app_date] => 2023-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1321 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -3 [patent_words_short_claim] => 230 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18351765 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/351765
Superscalar delay optimization with divided issue queue Jul 12, 2023 Issued
Array ( [id] => 18973891 [patent_doc_number] => 20240053983 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-15 [patent_title] => Performance Optimized Task Duplication and Migration [patent_app_type] => utility [patent_app_number] => 18/220536 [patent_app_country] => US [patent_app_date] => 2023-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6805 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18220536 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/220536
Performance Optimized Task Duplication and Migration Jul 10, 2023 Pending
Array ( [id] => 18741707 [patent_doc_number] => 20230350688 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-02 [patent_title] => VECTOR INSTRUCTION WITH PRECISE INTERRUPTS AND/OR OVERWRITES [patent_app_type] => utility [patent_app_number] => 18/350729 [patent_app_country] => US [patent_app_date] => 2023-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4505 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18350729 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/350729
VECTOR INSTRUCTION WITH PRECISE INTERRUPTS AND/OR OVERWRITES Jul 10, 2023 Pending
Array ( [id] => 20145584 [patent_doc_number] => 12379926 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-08-05 [patent_title] => Image processing apparatus with multibank registers for storing source, destination, and setting information for operational circuits [patent_app_type] => utility [patent_app_number] => 18/350022 [patent_app_country] => US [patent_app_date] => 2023-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2424 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 540 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18350022 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/350022
Image processing apparatus with multibank registers for storing source, destination, and setting information for operational circuits Jul 10, 2023 Issued
Array ( [id] => 18741732 [patent_doc_number] => 20230350713 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-02 [patent_title] => PARALLEL PROCESSING ARCHITECTURE WITH COUNTDOWN TAGGING [patent_app_type] => utility [patent_app_number] => 18/220331 [patent_app_country] => US [patent_app_date] => 2023-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16199 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18220331 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/220331
PARALLEL PROCESSING ARCHITECTURE WITH COUNTDOWN TAGGING Jul 10, 2023 Pending
Array ( [id] => 19685985 [patent_doc_number] => 20250004530 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-02 [patent_title] => LIMITED BIT TOGGLING FOR DATA BUS INVERSION [patent_app_type] => utility [patent_app_number] => 18/345940 [patent_app_country] => US [patent_app_date] => 2023-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4503 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18345940 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/345940
LIMITED BIT TOGGLING FOR DATA BUS INVERSION Jun 29, 2023 Pending
Array ( [id] => 18727859 [patent_doc_number] => 20230342152 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-26 [patent_title] => PARALLEL PROCESSING ARCHITECTURE WITH SPLIT CONTROL WORD CACHES [patent_app_type] => utility [patent_app_number] => 18/215866 [patent_app_country] => US [patent_app_date] => 2023-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19032 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 207 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18215866 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/215866
PARALLEL PROCESSING ARCHITECTURE WITH SPLIT CONTROL WORD CACHES Jun 28, 2023 Pending
Array ( [id] => 18846930 [patent_doc_number] => 20230409334 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-21 [patent_title] => PROVIDING CODE SECTIONS FOR MATRIX OF ARITHMETIC LOGIC UNITS IN A PROCESSOR [patent_app_type] => utility [patent_app_number] => 18/214385 [patent_app_country] => US [patent_app_date] => 2023-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 34684 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18214385 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/214385
PROVIDING CODE SECTIONS FOR MATRIX OF ARITHMETIC LOGIC UNITS IN A PROCESSOR Jun 25, 2023 Pending
Array ( [id] => 18711377 [patent_doc_number] => 20230334006 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-19 [patent_title] => COMPUTE NEAR MEMORY CONVOLUTION ACCELERATOR [patent_app_type] => utility [patent_app_number] => 18/212079 [patent_app_country] => US [patent_app_date] => 2023-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10165 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 204 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18212079 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/212079
COMPUTE NEAR MEMORY CONVOLUTION ACCELERATOR Jun 19, 2023 Pending
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