
David J. Huisman
Examiner (ID: 3471, Phone: (571)272-4168 , Office: P/2183 )
| Most Active Art Unit | 2183 |
| Art Unit(s) | 2183 |
| Total Applications | 955 |
| Issued Applications | 498 |
| Pending Applications | 139 |
| Abandoned Applications | 343 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 20709467
[patent_doc_number] => 20260133801
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2026-05-14
[patent_title] => COMPACT REGISTER SPECIFIERS FOR COMPACT INSTRUCTION ENCODING
[patent_app_type] => utility
[patent_app_number] => 19/352431
[patent_app_country] => US
[patent_app_date] => 2025-10-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 0
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 77
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19352431
[rel_patent_id] =>[rel_patent_doc_number] =>) 19/352431 | COMPACT REGISTER SPECIFIERS FOR COMPACT INSTRUCTION ENCODING | Oct 6, 2025 | Pending |
Array
(
[id] => 20380424
[patent_doc_number] => 20250362917
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-11-27
[patent_title] => CPU CAPABLE OF QUICKLY PROCESSING MEMORY COPY INSTRUCTION AND METHOD THEREFOR
[patent_app_type] => utility
[patent_app_number] => 19/290425
[patent_app_country] => US
[patent_app_date] => 2025-08-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 0
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -13
[patent_words_short_claim] => 310
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19290425
[rel_patent_id] =>[rel_patent_doc_number] =>) 19/290425 | CPU CAPABLE OF QUICKLY PROCESSING MEMORY COPY INSTRUCTION AND METHOD THEREFOR | Aug 4, 2025 | Pending |
Array
(
[id] => 20365899
[patent_doc_number] => 20250355711
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-11-20
[patent_title] => RE-ROUNDING IN INTEGRATED CIRCUIT FOR VARIANCE REDUCTION IN AI OPERATIONS
[patent_app_type] => utility
[patent_app_number] => 19/210276
[patent_app_country] => US
[patent_app_date] => 2025-05-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 15654
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 165
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19210276
[rel_patent_id] =>[rel_patent_doc_number] =>) 19/210276 | RE-ROUNDING IN INTEGRATED CIRCUIT FOR VARIANCE REDUCTION IN AI OPERATIONS | May 15, 2025 | Pending |
Array
(
[id] => 20137959
[patent_doc_number] => 20250245003
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-07-31
[patent_title] => Pipelined Decoding Microarchitecture Design Method for RISC-V Vector Instructions
[patent_app_type] => utility
[patent_app_number] => 19/008702
[patent_app_country] => US
[patent_app_date] => 2025-01-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 0
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -7
[patent_words_short_claim] => 533
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19008702
[rel_patent_id] =>[rel_patent_doc_number] =>) 19/008702 | Pipelined Decoding Microarchitecture Design Method for RISC-V Vector Instructions | Jan 2, 2025 | Pending |
Array
(
[id] => 19848858
[patent_doc_number] => 20250094209
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-03-20
[patent_title] => CONFIGURABLE CONTEXT SAVE AND RESTORE
[patent_app_type] => utility
[patent_app_number] => 18/959787
[patent_app_country] => US
[patent_app_date] => 2024-11-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6346
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -16
[patent_words_short_claim] => 97
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18959787
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/959787 | CONFIGURABLE CONTEXT SAVE AND RESTORE | Nov 25, 2024 | Pending |
Array
(
[id] => 20680354
[patent_doc_number] => 20260119173
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2026-04-30
[patent_title] => GATHER OPERATION USING A COMMON REGISTER FILE ENTRY AS DESTINATION REGISTER FOR ALL LOAD SUBOPERATIONS
[patent_app_type] => utility
[patent_app_number] => 18/933952
[patent_app_country] => US
[patent_app_date] => 2024-10-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 0
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -16
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18933952
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/933952 | GATHER OPERATION USING A COMMON REGISTER FILE ENTRY AS DESTINATION REGISTER FOR ALL LOAD SUBOPERATIONS | Oct 30, 2024 | Pending |
Array
(
[id] => 19864555
[patent_doc_number] => 20250103341
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-03-27
[patent_title] => BUS FOR TRANSPORTING OUTPUT VALUES OF NEURAL NETWORK LAYER
[patent_app_type] => utility
[patent_app_number] => 18/824034
[patent_app_country] => US
[patent_app_date] => 2024-09-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 31601
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -19
[patent_words_short_claim] => 166
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18824034
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/824034 | BUS FOR TRANSPORTING OUTPUT VALUES OF NEURAL NETWORK LAYER | Sep 3, 2024 | Pending |
Array
(
[id] => 19819027
[patent_doc_number] => 20250077234
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-03-06
[patent_title] => EXECUTION METHOD FOR INSTRUCTION CONFLICT, INSTRUCTION PROCESSING MODULE AND PROCESSOR
[patent_app_type] => utility
[patent_app_number] => 18/819125
[patent_app_country] => US
[patent_app_date] => 2024-08-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5545
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 83
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18819125
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/819125 | EXECUTION METHOD FOR INSTRUCTION CONFLICT, INSTRUCTION PROCESSING MODULE AND PROCESSOR | Aug 28, 2024 | Pending |
Array
(
[id] => 20513373
[patent_doc_number] => 20260037474
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2026-02-05
[patent_title] => COMPUTE-NEAR-MEMORY-SYSTEM EVENT HARDWARE PERFORMING A REDUCTION OPERATION
[patent_app_type] => utility
[patent_app_number] => 18/790925
[patent_app_country] => US
[patent_app_date] => 2024-07-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 18125
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 200
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18790925
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/790925 | COMPUTE-NEAR-MEMORY-SYSTEM EVENT HARDWARE PERFORMING A REDUCTION OPERATION | Jul 30, 2024 | Pending |
Array
(
[id] => 19530203
[patent_doc_number] => 20240354105
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-10-24
[patent_title] => APPARATUS AND METHOD FOR PERFORMING A SPLICE OPERATION
[patent_app_type] => utility
[patent_app_number] => 18/762800
[patent_app_country] => US
[patent_app_date] => 2024-07-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9375
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 311
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18762800
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/762800 | APPARATUS AND METHOD FOR PERFORMING A SPLICE OPERATION | Jul 2, 2024 | Pending |
Array
(
[id] => 19695021
[patent_doc_number] => 20250013566
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-01-09
[patent_title] => ALLOCATION OF THREAD LOCAL STORAGE WHEN A THREAD SWITCHES BETWEEN LINK DOMAINS SHARING A COMMON ADDRESS SPACE
[patent_app_type] => utility
[patent_app_number] => 18/763532
[patent_app_country] => US
[patent_app_date] => 2024-07-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5548
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 162
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18763532
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/763532 | ALLOCATION OF THREAD LOCAL STORAGE WHEN A THREAD SWITCHES BETWEEN LINK DOMAINS SHARING A COMMON ADDRESS SPACE | Jul 2, 2024 | Pending |
Array
(
[id] => 19588282
[patent_doc_number] => 20240385839
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-11-21
[patent_title] => PROCESSING METHOD OF MIXED PRECISION OPERATION AND INSTRUCTION PROCESSING APPARATUS
[patent_app_type] => utility
[patent_app_number] => 18/665108
[patent_app_country] => US
[patent_app_date] => 2024-05-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8584
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -12
[patent_words_short_claim] => 81
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18665108
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/665108 | PROCESSING METHOD OF MIXED PRECISION OPERATION AND INSTRUCTION PROCESSING APPARATUS | May 14, 2024 | Pending |
Array
(
[id] => 20351606
[patent_doc_number] => 20250348458
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-11-13
[patent_title] => MACROPROCESSOR ARCHITECTURES
[patent_app_type] => utility
[patent_app_number] => 18/656824
[patent_app_country] => US
[patent_app_date] => 2024-05-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 11709
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -19
[patent_words_short_claim] => 59
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18656824
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/656824 | MACROPROCESSOR ARCHITECTURES | May 6, 2024 | Abandoned |
Array
(
[id] => 19362940
[patent_doc_number] => 20240264974
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-08-08
[patent_title] => PARALLEL PROCESSING HAZARD MITIGATION AVOIDANCE
[patent_app_type] => utility
[patent_app_number] => 18/640044
[patent_app_country] => US
[patent_app_date] => 2024-04-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 24770
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -23
[patent_words_short_claim] => 142
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18640044
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/640044 | PARALLEL PROCESSING HAZARD MITIGATION AVOIDANCE | Apr 18, 2024 | Pending |
Array
(
[id] => 19864765
[patent_doc_number] => 20250103551
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-03-27
[patent_title] => Interleave Execution Circuit
[patent_app_type] => utility
[patent_app_number] => 18/628460
[patent_app_country] => US
[patent_app_date] => 2024-04-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 24872
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 100
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18628460
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/628460 | Interleave Execution Circuit | Apr 4, 2024 | Pending |
Array
(
[id] => 19320207
[patent_doc_number] => 20240241751
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-07-18
[patent_title] => MULTI-PHASED AND MULTI-THREADED PROGRAM EXECUTION BASED ON SIMD RATIO
[patent_app_type] => utility
[patent_app_number] => 18/623181
[patent_app_country] => US
[patent_app_date] => 2024-04-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 3120
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -15
[patent_words_short_claim] => 126
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18623181
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/623181 | MULTI-PHASED AND MULTI-THREADED PROGRAM EXECUTION BASED ON SIMD RATIO | Mar 31, 2024 | Pending |
Array
(
[id] => 20281704
[patent_doc_number] => 20250306946
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-10-02
[patent_title] => INDEPENDENT PROGRESS OF LANES IN A VECTOR PROCESSOR
[patent_app_type] => utility
[patent_app_number] => 18/618939
[patent_app_country] => US
[patent_app_date] => 2024-03-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4741
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 134
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18618939
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/618939 | INDEPENDENT PROGRESS OF LANES IN A VECTOR PROCESSOR | Mar 26, 2024 | Pending |
Array
(
[id] => 19283776
[patent_doc_number] => 20240220252
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-07-04
[patent_title] => INTERCONNECT DEVICE, OPERATION METHOD OF INTERCONNECT DEVICE, AND ARTIFICIAL INTELLIGENCE (AI) ACCELERATOR SYSTEM INCLUDING INTERCONNECT DEVICE
[patent_app_type] => utility
[patent_app_number] => 18/609501
[patent_app_country] => US
[patent_app_date] => 2024-03-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10915
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18609501
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/609501 | INTERCONNECT DEVICE, OPERATION METHOD OF INTERCONNECT DEVICE, AND ARTIFICIAL INTELLIGENCE (AI) ACCELERATOR SYSTEM INCLUDING INTERCONNECT DEVICE | Mar 18, 2024 | Pending |
Array
(
[id] => 19219881
[patent_doc_number] => 20240184585
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-06-06
[patent_title] => BFLOAT16 COMPARISON INSTRUCTIONS
[patent_app_type] => utility
[patent_app_number] => 18/436982
[patent_app_country] => US
[patent_app_date] => 2024-02-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 16483
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -26
[patent_words_short_claim] => 128
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18436982
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/436982 | BFLOAT16 COMPARISON INSTRUCTIONS | Feb 7, 2024 | Pending |
Array
(
[id] => 19144418
[patent_doc_number] => 20240143331
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-05-02
[patent_title] => COMPUTATION PROCESSING APPARATUS AND METHOD OF PROCESSING COMPUTATION
[patent_app_type] => utility
[patent_app_number] => 18/411185
[patent_app_country] => US
[patent_app_date] => 2024-01-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7772
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => 0
[patent_words_short_claim] => 86
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18411185
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/411185 | COMPUTATION PROCESSING APPARATUS AND METHOD OF PROCESSING COMPUTATION | Jan 11, 2024 | Pending |