David J. Huisman

Array ( [id] => 16314714 [patent_doc_number] => 20200293452 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-09-17 [patent_title] => MEMORY DEVICE AND METHOD INCLUDING CIRCULAR INSTRUCTION MEMORY QUEUE [patent_app_type] => utility [patent_app_number] => 16/814236 [patent_app_country] => US [patent_app_date] => 2020-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10745 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16814236 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16095383 [patent_doc_number] => 20200201678 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-06-25 [patent_title] => Multi-Phased and Multi-Threaded Program Execution Based on SIMD Ratio [patent_app_type] => utility [patent_app_number] => 16/805727 [patent_app_country] => US [patent_app_date] => 2020-02-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3089 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16805727 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19925169 [patent_doc_number] => 12299455 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2025-05-13 [patent_title] => Reconfigurable interconnect with multiplexer for flexible processor partitioning in a server computer [patent_app_type] => utility [patent_app_number] => 16/795264 [patent_app_country] => US [patent_app_date] => 2020-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 15 [patent_no_of_words] => 7007 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 447 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16795264 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18154795 [patent_doc_number] => 11567773 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-01-31 [patent_title] => Memory controller and memory system for generating instruction set based on non-interleaving block group information [patent_app_type] => utility [patent_app_number] => 16/745810 [patent_app_country] => US [patent_app_date] => 2020-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 8358 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 300 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16745810 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16964828 [patent_doc_number] => 20210216327 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-15 [patent_title] => REACH MATRIX SCHEDULER CIRCUIT FOR SCHEDULING OF INSTRUCTIONS TO BE EXECUTED IN A PROCESSOR [patent_app_type] => utility [patent_app_number] => 16/738362 [patent_app_country] => US [patent_app_date] => 2020-01-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15115 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16738362 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19669817 [patent_doc_number] => 12182576 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-12-31 [patent_title] => Executing a composite scalar-vector VLIW instruction having a repeat field [patent_app_type] => utility [patent_app_number] => 16/731214 [patent_app_country] => US [patent_app_date] => 2019-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 6719 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 222 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16731214 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20673192 [patent_doc_number] => 12613704 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-04-28 [patent_title] => Reusing snapshots shared between restoration and recovery [patent_app_type] => utility [patent_app_number] => 16/721994 [patent_app_country] => US [patent_app_date] => 2019-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 45 [patent_figures_cnt] => 65 [patent_no_of_words] => 25993 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 495 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16721994 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15772897 [patent_doc_number] => 20200117466 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-16 [patent_title] => COMBINING INSTRUCTIONS FROM DIFFERENT BRANCHES FOR EXECUTION IN A SINGLE N-WAY VLIW PROCESSING ELEMENT OF A MULTITHREADED PROCESSOR [patent_app_type] => utility [patent_app_number] => 16/712778 [patent_app_country] => US [patent_app_date] => 2019-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4525 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16712778 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16872187 [patent_doc_number] => 20210165654 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-03 [patent_title] => ELIMINATING EXECUTION OF INSTRUCTIONS THAT PRODUCE A CONSTANT RESULT [patent_app_type] => utility [patent_app_number] => 16/702446 [patent_app_country] => US [patent_app_date] => 2019-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3689 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16702446 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16017681 [patent_doc_number] => 20200183684 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-06-11 [patent_title] => ARITHMETIC PROCESSING APPARATUS AND METHOD OF CONTROLLING ARITHMETIC PROCESSING APPARATUS [patent_app_type] => utility [patent_app_number] => 16/701209 [patent_app_country] => US [patent_app_date] => 2019-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10573 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 203 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16701209 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15653931 [patent_doc_number] => 20200089496 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-03-19 [patent_title] => ARITHMETIC PROCESSING DEVICE, INFORMATION PROCESSING APPARATUS, AND METHOD FOR CONTROLLING ARITHMETIC PROCESSING DEVICE [patent_app_type] => utility [patent_app_number] => 16/689147 [patent_app_country] => US [patent_app_date] => 2019-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9090 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16689147 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17535363 [patent_doc_number] => 20220113972 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-04-14 [patent_title] => MICROPROCESSOR, AND OPERATION METHOD THEREFOR [patent_app_type] => utility [patent_app_number] => 17/428711 [patent_app_country] => US [patent_app_date] => 2019-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8883 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 38 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17428711 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17877331 [patent_doc_number] => 11449345 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-09-20 [patent_title] => Methods, systems and apparatus for adjusting a data path element of a neural network accelerator from convolution mode to pooling mode [patent_app_type] => utility [patent_app_number] => 16/687377 [patent_app_country] => US [patent_app_date] => 2019-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 25508 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 197 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16687377 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16826368 [patent_doc_number] => 20210141661 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-05-13 [patent_title] => Lightweight Context For CPU Idling Using A Real Time Kernel [patent_app_type] => utility [patent_app_number] => 16/680915 [patent_app_country] => US [patent_app_date] => 2019-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4296 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16680915 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15594261 [patent_doc_number] => 20200073665 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-03-05 [patent_title] => Method for Accessing Memory of Multi-Core System, Related Apparatus, System, and Storage Medium [patent_app_type] => utility [patent_app_number] => 16/677816 [patent_app_country] => US [patent_app_date] => 2019-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17561 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16677816 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18734775 [patent_doc_number] => 11803507 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-10-31 [patent_title] => Data stream protocol field decoding by a systolic array [patent_app_type] => utility [patent_app_number] => 16/654924 [patent_app_country] => US [patent_app_date] => 2019-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 10724 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16654924 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18561706 [patent_doc_number] => 11726950 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-15 [patent_title] => Compute near memory convolution accelerator [patent_app_type] => utility [patent_app_number] => 16/586975 [patent_app_country] => US [patent_app_date] => 2019-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 13 [patent_no_of_words] => 10130 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16586975 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17469137 [patent_doc_number] => 11275614 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-03-15 [patent_title] => Dynamic update of the number of architected registers assigned to software threads using spill counts [patent_app_type] => utility [patent_app_number] => 16/586185 [patent_app_country] => US [patent_app_date] => 2019-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 5876 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16586185 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16722169 [patent_doc_number] => 20210089316 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-25 [patent_title] => DEEP LEARNING IMPLEMENTATIONS USING SYSTOLIC ARRAYS AND FUSED OPERATIONS [patent_app_type] => utility [patent_app_number] => 16/582433 [patent_app_country] => US [patent_app_date] => 2019-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 26922 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16582433 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15531655 [patent_doc_number] => 20200058133 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-02-20 [patent_title] => METHOD TO COMPUTE SLIDING WINDOW BLOCK SUM USING INSTRUCTION BASED SELECTIVE HORIZONTAL ADDITION IN VECTOR PROCESSOR [patent_app_type] => utility [patent_app_number] => 16/552387 [patent_app_country] => US [patent_app_date] => 2019-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12227 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 198 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16552387 [rel_patent_id] =>[rel_patent_doc_number] =>)