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David J. Huisman

Examiner (ID: 3471, Phone: (571)272-4168 , Office: P/2183 )

Most Active Art Unit
2183
Art Unit(s)
2183
Total Applications
955
Issued Applications
498
Pending Applications
139
Abandoned Applications
343

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16675610 [patent_doc_number] => 20210064376 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-04 [patent_title] => LAST PHYSICAL REGISTER REFERENCE SCHEME [patent_app_type] => utility [patent_app_number] => 16/551208 [patent_app_country] => US [patent_app_date] => 2019-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7601 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16551208 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/551208
History file for previous register mapping storage and last reference indication Aug 25, 2019 Issued
Array ( [id] => 16675611 [patent_doc_number] => 20210064377 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-04 [patent_title] => EXECUTING INSTRUCTIONS BASED ON STATUS [patent_app_type] => utility [patent_app_number] => 16/550612 [patent_app_country] => US [patent_app_date] => 2019-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6208 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16550612 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/550612
Speculatively executing instructions that follow a status updating instruction Aug 25, 2019 Issued
Array ( [id] => 17143722 [patent_doc_number] => 20210311735 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-10-07 [patent_title] => VECTOR INSTRUCTION WITH PRECISE INTERRUPTS AND/OR OVERWRITES [patent_app_type] => utility [patent_app_number] => 17/266338 [patent_app_country] => US [patent_app_date] => 2019-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4454 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17266338 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/266338
VECTOR INSTRUCTION WITH PRECISE INTERRUPTS AND/OR OVERWRITES Aug 12, 2019 Abandoned
Array ( [id] => 19443424 [patent_doc_number] => 12093696 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2024-09-17 [patent_title] => Bus for transporting output values of a neural network layer to cores specified by configuration data [patent_app_type] => utility [patent_app_number] => 16/537481 [patent_app_country] => US [patent_app_date] => 2019-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 27 [patent_no_of_words] => 31426 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 311 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16537481 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/537481
Bus for transporting output values of a neural network layer to cores specified by configuration data Aug 8, 2019 Issued
Array ( [id] => 16224879 [patent_doc_number] => 20200249996 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-08-06 [patent_title] => SYSTEMS AND METHODS FOR ARTIFICIAL INTELLIGENCE HARDWARE PROCESSING [patent_app_type] => utility [patent_app_number] => 16/528543 [patent_app_country] => US [patent_app_date] => 2019-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13372 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16528543 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/528543
SYSTEMS AND METHODS FOR ARTIFICIAL INTELLIGENCE HARDWARE PROCESSING Jul 30, 2019 Abandoned
Array ( [id] => 15042825 [patent_doc_number] => 20190332417 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-10-31 [patent_title] => DELAYING BRANCH PREDICTION UPDATES UNTIL AFTER A TRANSACTION IS COMPLETED [patent_app_type] => utility [patent_app_number] => 16/507719 [patent_app_country] => US [patent_app_date] => 2019-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18090 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 248 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16507719 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/507719
Delaying branch prediction updates specified by a suspend branch prediction instruction until after a transaction is completed Jul 9, 2019 Issued
Array ( [id] => 15027491 [patent_doc_number] => 20190324750 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-10-24 [patent_title] => INSTRUCTIONS TO COUNT CONTIGUOUS REGISTER ELEMENTS HAVING SPECIFIC VALUES [patent_app_type] => utility [patent_app_number] => 16/503170 [patent_app_country] => US [patent_app_date] => 2019-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12118 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16503170 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/503170
Instructions to count a number of contiguous register elements having specific values in a selected location Jul 2, 2019 Issued
Array ( [id] => 15027489 [patent_doc_number] => 20190324749 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-10-24 [patent_title] => INSTRUCTIONS TO COUNT CONTIGUOUS REGISTER ELEMENTS HAVING SPECIFIC VALUES [patent_app_type] => utility [patent_app_number] => 16/503136 [patent_app_country] => US [patent_app_date] => 2019-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12404 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16503136 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/503136
Instructions to count a number of contiguous register elements having specific values in a selected location Jul 2, 2019 Issued
Array ( [id] => 16957823 [patent_doc_number] => 11061684 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-07-13 [patent_title] => Architecturally paired spill/reload multiple instructions for suppressing a snapshot latest value determination [patent_app_type] => utility [patent_app_number] => 16/458591 [patent_app_country] => US [patent_app_date] => 2019-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 45 [patent_figures_cnt] => 65 [patent_no_of_words] => 30737 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16458591 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/458591
Architecturally paired spill/reload multiple instructions for suppressing a snapshot latest value determination Jun 30, 2019 Issued
Array ( [id] => 16514781 [patent_doc_number] => 20200394039 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-12-17 [patent_title] => Processor with Multiple Load Queues [patent_app_type] => utility [patent_app_number] => 16/437739 [patent_app_country] => US [patent_app_date] => 2019-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12483 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16437739 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/437739
Processor with multiple load queues including a queue to manage ordering and a queue to manage replay Jun 10, 2019 Issued
Array ( [id] => 18046634 [patent_doc_number] => 11520588 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-12-06 [patent_title] => Prefetch filter table for storing moderately-confident entries evicted from a history table [patent_app_type] => utility [patent_app_number] => 16/435651 [patent_app_country] => US [patent_app_date] => 2019-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 9818 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 269 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16435651 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/435651
Prefetch filter table for storing moderately-confident entries evicted from a history table Jun 9, 2019 Issued
Array ( [id] => 14840409 [patent_doc_number] => 20190278605 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-09-12 [patent_title] => SOFTWARE-CONTROLLED VARIABLE WAVEFRONT SIZE EXECUTION AT GPU [patent_app_type] => utility [patent_app_number] => 16/425625 [patent_app_country] => US [patent_app_date] => 2019-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10167 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16425625 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/425625
SOFTWARE-CONTROLLED VARIABLE WAVEFRONT SIZE EXECUTION AT GPU May 28, 2019 Pending
Array ( [id] => 16826351 [patent_doc_number] => 20210141644 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-05-13 [patent_title] => ASYNCHRONOUS PROCESSOR ARCHITECTURE [patent_app_type] => utility [patent_app_number] => 17/255791 [patent_app_country] => US [patent_app_date] => 2019-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10359 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 291 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17255791 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/255791
ASYNCHRONOUS PROCESSOR ARCHITECTURE May 20, 2019 Pending
Array ( [id] => 18592005 [patent_doc_number] => 11740903 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-29 [patent_title] => Computing machine using a matrix space and matrix pointer registers for matrix and array processing [patent_app_type] => utility [patent_app_number] => 16/396680 [patent_app_country] => US [patent_app_date] => 2019-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 13808 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 321 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16396680 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/396680
Computing machine using a matrix space and matrix pointer registers for matrix and array processing Apr 26, 2019 Issued
Array ( [id] => 14719699 [patent_doc_number] => 20190250913 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-08-15 [patent_title] => PROCESSOR FOR AVOIDING REDUCED PERFORMANCE USING INSTRUCTION METADATA TO DETERMINE NOT TO MAINTAIN A MAPPING OF A LOGICAL REGISTER TO A PHYSICAL REGISTER IN A FIRST LEVEL REGISTER FILE [patent_app_type] => utility [patent_app_number] => 16/395693 [patent_app_country] => US [patent_app_date] => 2019-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11676 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16395693 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/395693
Processor for avoiding reduced performance using instruction metadata to determine not to maintain a mapping of a logical register to a physical register in a first level register file Apr 25, 2019 Issued
Array ( [id] => 15120939 [patent_doc_number] => 20190347102 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-11-14 [patent_title] => ARITHMETIC PROCESSING APPARATUS AND CONTROL METHOD FOR ARITHMETIC PROCESSING APPARATUS [patent_app_type] => utility [patent_app_number] => 16/392677 [patent_app_country] => US [patent_app_date] => 2019-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15513 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16392677 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/392677
ARITHMETIC PROCESSING APPARATUS AND CONTROL METHOD FOR ARITHMETIC PROCESSING APPARATUS Apr 23, 2019 Abandoned
Array ( [id] => 17801957 [patent_doc_number] => 11416257 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-08-16 [patent_title] => Hybrid and aggregrate branch prediction system with a tagged branch orientation predictor for prediction override or pass-through [patent_app_type] => utility [patent_app_number] => 16/380737 [patent_app_country] => US [patent_app_date] => 2019-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5968 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16380737 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/380737
Hybrid and aggregrate branch prediction system with a tagged branch orientation predictor for prediction override or pass-through Apr 9, 2019 Issued
Array ( [id] => 15151781 [patent_doc_number] => 20190354368 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-11-21 [patent_title] => ARITHMETIC PROCESSING APPARATUS AND CONTROL METHOD FOR ARITHMETIC PROCESSING APPARATUS [patent_app_type] => utility [patent_app_number] => 16/378037 [patent_app_country] => US [patent_app_date] => 2019-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17674 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16378037 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/378037
ARITHMETIC PROCESSING APPARATUS AND CONTROL METHOD FOR ARITHMETIC PROCESSING APPARATUS Apr 7, 2019 Abandoned
Array ( [id] => 18104178 [patent_doc_number] => 11544064 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-01-03 [patent_title] => Processor for executing a loop acceleration instruction to start and end a loop [patent_app_type] => utility [patent_app_number] => 16/479361 [patent_app_country] => US [patent_app_date] => 2019-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 2229 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 381 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16479361 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/479361
Processor for executing a loop acceleration instruction to start and end a loop Apr 7, 2019 Issued
Array ( [id] => 18000034 [patent_doc_number] => 11501142 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-11-15 [patent_title] => Tiling control circuit for downloading and processing an input tile based on source and destination buffer availability [patent_app_type] => utility [patent_app_number] => 16/374451 [patent_app_country] => US [patent_app_date] => 2019-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 5860 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16374451 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/374451
Tiling control circuit for downloading and processing an input tile based on source and destination buffer availability Apr 2, 2019 Issued
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