David J. Huisman

Array ( [id] => 14935041 [patent_doc_number] => 20190303158 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-10-03 [patent_title] => TRAINING AND UTILIZATION OF A NEURAL BRANCH PREDICTOR [patent_app_type] => utility [patent_app_number] => 15/940896 [patent_app_country] => US [patent_app_date] => 2018-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7250 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -26 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15940896 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13483059 [patent_doc_number] => 20180293072 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-10-11 [patent_title] => METHOD AND APPARATUS FOR DETECTING NOP SLED [patent_app_type] => utility [patent_app_number] => 15/933522 [patent_app_country] => US [patent_app_date] => 2018-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5598 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15933522 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17121094 [patent_doc_number] => 11132228 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-09-28 [patent_title] => SMT processor to create a virtual vector register file for a borrower thread from a number of donated vector register files [patent_app_type] => utility [patent_app_number] => 15/927842 [patent_app_country] => US [patent_app_date] => 2018-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 9187 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15927842 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16446800 [patent_doc_number] => 10838729 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-11-17 [patent_title] => System and method for predicting memory dependence when a source register of a push instruction matches the destination register of a pop instruction [patent_app_type] => utility [patent_app_number] => 15/927501 [patent_app_country] => US [patent_app_date] => 2018-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 11867 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15927501 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14901355 [patent_doc_number] => 20190294443 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-09-26 [patent_title] => PROVIDING EARLY PIPELINE OPTIMIZATION OF CONDITIONAL INSTRUCTIONS IN PROCESSOR-BASED SYSTEMS [patent_app_type] => utility [patent_app_number] => 15/926429 [patent_app_country] => US [patent_app_date] => 2018-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6063 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15926429 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13432513 [patent_doc_number] => 20180267799 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-09-20 [patent_title] => MICROPROCESSOR SYSTEM AND METHOD THEREFOR [patent_app_type] => utility [patent_app_number] => 15/918312 [patent_app_country] => US [patent_app_date] => 2018-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7524 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15918312 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18703231 [patent_doc_number] => 11789741 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-10-17 [patent_title] => Determining an optimum quantity of interleaved instruction streams of defined coroutines [patent_app_type] => utility [patent_app_number] => 15/915787 [patent_app_country] => US [patent_app_date] => 2018-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8370 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 330 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15915787 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17308982 [patent_doc_number] => 11210092 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-12-28 [patent_title] => Servicing indirect data storage requests with multiple memory controllers [patent_app_type] => utility [patent_app_number] => 15/912960 [patent_app_country] => US [patent_app_date] => 2018-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5664 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 221 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15912960 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13467543 [patent_doc_number] => 20180285314 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-10-04 [patent_title] => ARITHMETIC PROCESSING DEVICE, INFORMATION PROCESSING APPARATUS, AND METHOD FOR CONTROLLING ARITHMETIC PROCESSING DEVICE [patent_app_type] => utility [patent_app_number] => 15/910029 [patent_app_country] => US [patent_app_date] => 2018-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9105 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15910029 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17817204 [patent_doc_number] => 11422815 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-08-23 [patent_title] => System and method for field programmable gate array-assisted binary translation [patent_app_type] => utility [patent_app_number] => 15/909936 [patent_app_country] => US [patent_app_date] => 2018-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 4956 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 219 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15909936 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17194825 [patent_doc_number] => 11163578 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-11-02 [patent_title] => Systems and methods for reducing register bank conflicts based on a software hint bit causing a hardware thread switch [patent_app_type] => utility [patent_app_number] => 15/903549 [patent_app_country] => US [patent_app_date] => 2018-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 25 [patent_no_of_words] => 18266 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15903549 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14782151 [patent_doc_number] => 20190265973 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-08-29 [patent_title] => Fusion of SIMD Processing Units [patent_app_type] => utility [patent_app_number] => 15/903283 [patent_app_country] => US [patent_app_date] => 2018-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16483 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15903283 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14719707 [patent_doc_number] => 20190250917 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-08-15 [patent_title] => Range Mapping of Input Operands for Transcendental Functions [patent_app_type] => utility [patent_app_number] => 15/896582 [patent_app_country] => US [patent_app_date] => 2018-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7409 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15896582 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16145557 [patent_doc_number] => 10705849 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-07-07 [patent_title] => Mode-selectable processor for execution of a single thread in a first mode and plural borrowed threads in a second mode [patent_app_type] => utility [patent_app_number] => 15/888359 [patent_app_country] => US [patent_app_date] => 2018-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 5693 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15888359 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14218509 [patent_doc_number] => 20190121639 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-04-25 [patent_title] => PROCESSING IN NEURAL NETWORKS [patent_app_type] => utility [patent_app_number] => 15/886331 [patent_app_country] => US [patent_app_date] => 2018-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3577 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15886331 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18189301 [patent_doc_number] => 11579886 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-02-14 [patent_title] => System and method for multi-level classification of branches [patent_app_type] => utility [patent_app_number] => 15/865756 [patent_app_country] => US [patent_app_date] => 2018-01-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 8012 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 486 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15865756 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14570803 [patent_doc_number] => 20190213008 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-07-11 [patent_title] => SYSTEM AND METHOD FOR HARD-TO-PREDICT BRANCH DETECTION TO ENABLE LOW LATENCY MULTI-PATH BRANCH STREAM EXECUTION [patent_app_type] => utility [patent_app_number] => 15/865719 [patent_app_country] => US [patent_app_date] => 2018-01-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11214 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15865719 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12755980 [patent_doc_number] => 20180143827 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-24 [patent_title] => Operation Cell Data Processor Systems and Methods [patent_app_type] => utility [patent_app_number] => 15/844810 [patent_app_country] => US [patent_app_date] => 2017-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3978 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 32 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15844810 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17091640 [patent_doc_number] => 11119830 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-09-14 [patent_title] => Thread migration and shared cache fencing based on processor core temperature [patent_app_type] => utility [patent_app_number] => 15/844901 [patent_app_country] => US [patent_app_date] => 2017-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4761 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15844901 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17031497 [patent_doc_number] => 11093308 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-08-17 [patent_title] => System and method for sending messages to configure remote virtual endpoints in nodes of a systolic array [patent_app_type] => utility [patent_app_number] => 15/844487 [patent_app_country] => US [patent_app_date] => 2017-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 2410 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15844487 [rel_patent_id] =>[rel_patent_doc_number] =>)