Search

David J. Huisman

Examiner (ID: 10967, Phone: (571)272-4168 , Office: P/2183 )

Most Active Art Unit
2183
Art Unit(s)
2183
Total Applications
937
Issued Applications
493
Pending Applications
137
Abandoned Applications
337

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 12060812 [patent_doc_number] => 20170337156 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-11-23 [patent_title] => 'COMPUTING MACHINE ARCHITECTURE FOR MATRIX AND ARRAY PROCESSING' [patent_app_type] => utility [patent_app_number] => 15/488494 [patent_app_country] => US [patent_app_date] => 2017-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 5155 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15488494 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/488494
COMPUTING MACHINE ARCHITECTURE FOR MATRIX AND ARRAY PROCESSING Apr 15, 2017 Abandoned
Array ( [id] => 17454790 [patent_doc_number] => 11269649 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-03-08 [patent_title] => Resuming beats of processing of a suspended vector instruction based on beat status information indicating completed beats [patent_app_type] => utility [patent_app_number] => 16/078780 [patent_app_country] => US [patent_app_date] => 2017-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 19 [patent_no_of_words] => 16390 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 265 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16078780 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/078780
Resuming beats of processing of a suspended vector instruction based on beat status information indicating completed beats Mar 16, 2017 Issued
Array ( [id] => 16986903 [patent_doc_number] => 11074075 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-07-27 [patent_title] => Wait instruction for preventing execution of one or more instructions until a load counter or store counter reaches a specified value [patent_app_type] => utility [patent_app_number] => 15/442412 [patent_app_country] => US [patent_app_date] => 2017-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3392 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15442412 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/442412
Wait instruction for preventing execution of one or more instructions until a load counter or store counter reaches a specified value Feb 23, 2017 Issued
Array ( [id] => 13721419 [patent_doc_number] => 20170371664 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-12-28 [patent_title] => PROGRAM INFORMATION GENERATION SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT [patent_app_type] => utility [patent_app_number] => 15/440635 [patent_app_country] => US [patent_app_date] => 2017-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7921 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15440635 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/440635
PROGRAM INFORMATION GENERATION SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT Feb 22, 2017 Abandoned
Array ( [id] => 15106287 [patent_doc_number] => 10474468 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-11-12 [patent_title] => Indicating instruction scheduling mode for processing wavefront portions [patent_app_type] => utility [patent_app_number] => 15/439540 [patent_app_country] => US [patent_app_date] => 2017-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5154 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15439540 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/439540
Indicating instruction scheduling mode for processing wavefront portions Feb 21, 2017 Issued
Array ( [id] => 11672248 [patent_doc_number] => 20170160970 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-08 [patent_title] => 'DATA STORAGE RESOURCE ALLOCATION USING CATEGORY BLACKLISTING WHEN DATA MANAGEMENT REQUESTS FAIL' [patent_app_type] => utility [patent_app_number] => 15/438347 [patent_app_country] => US [patent_app_date] => 2017-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8882 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15438347 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/438347
DATA STORAGE RESOURCE ALLOCATION USING CATEGORY BLACKLISTING WHEN DATA MANAGEMENT REQUESTS FAIL Feb 20, 2017 Abandoned
Array ( [id] => 11672249 [patent_doc_number] => 20170160971 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-08 [patent_title] => 'DATA STORAGE RESOURCE ALLOCATION USING BLACKLISTING OF DATA STORAGE REQUESTS CLASSIFIED IN THE SAME CATEGORY AS A DATA STORAGE REQUEST THAT IS DETERMINED TO FAIL IF ATTEMPTED' [patent_app_type] => utility [patent_app_number] => 15/438433 [patent_app_country] => US [patent_app_date] => 2017-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8900 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15438433 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/438433
Data storage resource allocation using blacklisting of data storage requests classified in the same category as a data storage request that is determined to fail if attempted Feb 20, 2017 Issued
Array ( [id] => 16431455 [patent_doc_number] => 10831537 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-11-10 [patent_title] => Dynamic update of the number of architected registers assigned to software threads using spill counts [patent_app_type] => utility [patent_app_number] => 15/435803 [patent_app_country] => US [patent_app_date] => 2017-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 5846 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 264 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15435803 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/435803
Dynamic update of the number of architected registers assigned to software threads using spill counts Feb 16, 2017 Issued
Array ( [id] => 13361391 [patent_doc_number] => 20180232235 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-08-16 [patent_title] => EFFICIENT HARDWARE-BASED EXTRACTION OF PROGRAM INSTRUCTIONS FOR CRITICAL PATHS [patent_app_type] => utility [patent_app_number] => 15/433674 [patent_app_country] => US [patent_app_date] => 2017-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17155 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15433674 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/433674
Efficient hardware-based extraction of program instructions for critical paths Feb 14, 2017 Issued
Array ( [id] => 11665172 [patent_doc_number] => 20170153891 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-01 [patent_title] => 'DATA PROCESSING APPARATUS AND METHOD' [patent_app_type] => utility [patent_app_number] => 15/431955 [patent_app_country] => US [patent_app_date] => 2017-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 18077 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15431955 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/431955
Data processing apparatus and method for processing a SIMD instruction specifying a control value having a first portion identifying a selected data size and a second portion identifying at least one control parameter having a number of bits that varies in dependence on a number of bits comprised by the first portion Feb 13, 2017 Issued
Array ( [id] => 17252766 [patent_doc_number] => 11188254 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-11-30 [patent_title] => Using a data mover and a clone blocklist primitive to clone files on a virtual file system [patent_app_type] => utility [patent_app_number] => 15/409294 [patent_app_country] => US [patent_app_date] => 2017-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 11999 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 350 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15409294 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/409294
Using a data mover and a clone blocklist primitive to clone files on a virtual file system Jan 17, 2017 Issued
Array ( [id] => 11672384 [patent_doc_number] => 20170161106 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-08 [patent_title] => 'PROVIDING THREAD FAIRNESS IN A HYPER-THREADED MICROPROCESSOR' [patent_app_type] => utility [patent_app_number] => 15/385823 [patent_app_country] => US [patent_app_date] => 2016-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5887 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15385823 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/385823
PROVIDING THREAD FAIRNESS IN A HYPER-THREADED MICROPROCESSOR Dec 19, 2016 Abandoned
Array ( [id] => 14047337 [patent_doc_number] => 20190079775 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-03-14 [patent_title] => DATA PROCESSING [patent_app_type] => utility [patent_app_number] => 15/781001 [patent_app_country] => US [patent_app_date] => 2016-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12594 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15781001 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/781001
Apparatus for preventing rescheduling of a paused thread based on instruction classification Nov 29, 2016 Issued
Array ( [id] => 11501432 [patent_doc_number] => 20170075617 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-03-16 [patent_title] => 'INSTANTIATING A VIRTUAL MACHINE WITH A VIRTUAL NON-UNIFORM MEMORY ARCHITECTURE' [patent_app_type] => utility [patent_app_number] => 15/359561 [patent_app_country] => US [patent_app_date] => 2016-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 10040 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15359561 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/359561
Instantiating a virtual machine with a virtual non-uniform memory architecture and determining a highest detected NUMA ratio in a datacenter Nov 21, 2016 Issued
Array ( [id] => 11494377 [patent_doc_number] => 20170068562 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-03-09 [patent_title] => 'VIRTUAL NON-UNIFORM MEMORY ARCHITECTURE FOR VIRTUAL MACHINES' [patent_app_type] => utility [patent_app_number] => 15/355754 [patent_app_country] => US [patent_app_date] => 2016-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 12522 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15355754 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/355754
Adjusting guest memory allocation in virtual non-uniform memory architecture (NUMA) nodes of a virtual machine Nov 17, 2016 Issued
Array ( [id] => 14704213 [patent_doc_number] => 10379853 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-08-13 [patent_title] => Sliding window encoding methods for executing vector compare instructions to write distance and match information to different sections of the same register [patent_app_type] => utility [patent_app_number] => 15/346655 [patent_app_country] => US [patent_app_date] => 2016-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 23 [patent_no_of_words] => 15451 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15346655 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/346655
Sliding window encoding methods for executing vector compare instructions to write distance and match information to different sections of the same register Nov 7, 2016 Issued
Array ( [id] => 12611808 [patent_doc_number] => 20180095766 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-04-05 [patent_title] => FLUSHING IN A PARALLELIZED PROCESSOR [patent_app_type] => utility [patent_app_number] => 15/285555 [patent_app_country] => US [patent_app_date] => 2016-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5856 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -24 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15285555 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/285555
FLUSHING IN A PARALLELIZED PROCESSOR Oct 4, 2016 Abandoned
Array ( [id] => 16864491 [patent_doc_number] => 11023231 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-06-01 [patent_title] => Systems and methods for executing a fused multiply-add instruction for complex numbers [patent_app_type] => utility [patent_app_number] => 15/283384 [patent_app_country] => US [patent_app_date] => 2016-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 28 [patent_no_of_words] => 19962 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 207 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15283384 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/283384
Systems and methods for executing a fused multiply-add instruction for complex numbers Sep 30, 2016 Issued
Array ( [id] => 17252765 [patent_doc_number] => 11188253 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-11-30 [patent_title] => Using a data mover and a zero blocklist primitive to zero files on a virtual file system [patent_app_type] => utility [patent_app_number] => 15/263202 [patent_app_country] => US [patent_app_date] => 2016-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 11990 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 283 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15263202 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/263202
Using a data mover and a zero blocklist primitive to zero files on a virtual file system Sep 11, 2016 Issued
Array ( [id] => 11314095 [patent_doc_number] => 20160350205 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-12-01 [patent_title] => 'CONCURRENT EXECUTION OF A FIRST INSTANCE AND A CLONED INSTANCE OF AN APPLICATION' [patent_app_type] => utility [patent_app_number] => 15/236919 [patent_app_country] => US [patent_app_date] => 2016-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 9198 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15236919 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/236919
CONCURRENT EXECUTION OF A FIRST INSTANCE AND A CLONED INSTANCE OF AN APPLICATION Aug 14, 2016 Abandoned
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