Search

David J. Huisman

Examiner (ID: 10967, Phone: (571)272-4168 , Office: P/2183 )

Most Active Art Unit
2183
Art Unit(s)
2183
Total Applications
937
Issued Applications
493
Pending Applications
137
Abandoned Applications
337

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 14395153 [patent_doc_number] => 10310860 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-06-04 [patent_title] => Starting and stopping instruction dispatch to execution unit queues in a multi-pipeline processor [patent_app_type] => utility [patent_app_number] => 15/224213 [patent_app_country] => US [patent_app_date] => 2016-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 4455 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15224213 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/224213
Starting and stopping instruction dispatch to execution unit queues in a multi-pipeline processor Jul 28, 2016 Issued
Array ( [id] => 11423542 [patent_doc_number] => 20170031685 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-02-02 [patent_title] => 'APPARATUS WITH REDUCED HARDWARE REGISTER SET' [patent_app_type] => utility [patent_app_number] => 15/222994 [patent_app_country] => US [patent_app_date] => 2016-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 12926 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15222994 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/222994
APPARATUS WITH REDUCED HARDWARE REGISTER SET Jul 28, 2016 Abandoned
Array ( [id] => 11272547 [patent_doc_number] => 20160335094 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-11-17 [patent_title] => 'Apparatus and Method for Activating and Shutting Down Enhanced Pipeline Stages and Enhanced Modules Based on Priority and Performance Requirements' [patent_app_type] => utility [patent_app_number] => 15/224410 [patent_app_country] => US [patent_app_date] => 2016-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7152 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15224410 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/224410
Apparatus and method for activating and shutting down enhanced pipeline stages and enhanced modules based on priority and performance requirements Jul 28, 2016 Issued
Array ( [id] => 12025715 [patent_doc_number] => 20170315814 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-11-02 [patent_title] => 'OUT-OF-ORDER BLOCK-BASED PROCESSORS AND INSTRUCTION SCHEDULERS' [patent_app_type] => utility [patent_app_number] => 15/224469 [patent_app_country] => US [patent_app_date] => 2016-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 17167 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15224469 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/224469
Out-of-order block-based processors and instruction schedulers using ready state data indexed by instruction position identifiers Jul 28, 2016 Issued
Array ( [id] => 11272668 [patent_doc_number] => 20160335215 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-11-17 [patent_title] => 'ACCELERATOR ENGINE COMMANDS SUBMISSION OVER AN INTERCONNECT LINK' [patent_app_type] => utility [patent_app_number] => 15/222823 [patent_app_country] => US [patent_app_date] => 2016-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3249 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15222823 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/222823
Methods for the submission of accelerator commands and corresponding command structures to remote hardware accelerator engines over an interconnect link Jul 27, 2016 Issued
Array ( [id] => 19369820 [patent_doc_number] => 12061906 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-08-13 [patent_title] => Apparatus and method for performing a splice of vectors based on location and length data [patent_app_type] => utility [patent_app_number] => 15/745478 [patent_app_country] => US [patent_app_date] => 2016-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 13 [patent_no_of_words] => 8052 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 463 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15745478 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/745478
Apparatus and method for performing a splice of vectors based on location and length data Jun 14, 2016 Issued
Array ( [id] => 13679501 [patent_doc_number] => 20160378487 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-12-29 [patent_title] => EFFICIENT INSTRUCTION FUSION BY FUSING INSTRUCTIONS THAT FALL WITHIN A COUNTER-TRACKED AMOUNT OF CYCLES APART [patent_app_type] => utility [patent_app_number] => 15/143518 [patent_app_country] => US [patent_app_date] => 2016-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3184 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -3 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15143518 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/143518
EFFICIENT INSTRUCTION FUSION BY FUSING INSTRUCTIONS THAT FALL WITHIN A COUNTER-TRACKED AMOUNT OF CYCLES APART Apr 29, 2016 Abandoned
Array ( [id] => 11049640 [patent_doc_number] => 20160246600 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-08-25 [patent_title] => 'EFFICIENT INSTRUCTION FUSION BY FUSING INSTRUCTIONS THAT FALL WITHIN A COUNTER-TRACKED AMOUNT OF CYCLES APART' [patent_app_type] => utility [patent_app_number] => 15/143522 [patent_app_country] => US [patent_app_date] => 2016-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3316 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15143522 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/143522
EFFICIENT INSTRUCTION FUSION BY FUSING INSTRUCTIONS THAT FALL WITHIN A COUNTER-TRACKED AMOUNT OF CYCLES APART Apr 29, 2016 Abandoned
Array ( [id] => 11365984 [patent_doc_number] => 20170003965 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-01-05 [patent_title] => 'EFFICIENT INSTRUCTION FUSION BY FUSING INSTRUCTIONS THAT FALL WITHIN A COUNTER-TRACKED AMOUNT OF CYCLES APART' [patent_app_type] => utility [patent_app_number] => 15/143520 [patent_app_country] => US [patent_app_date] => 2016-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3279 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15143520 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/143520
Multicore system for fusing instructions queued during a dynamically adjustable time window Apr 29, 2016 Issued
Array ( [id] => 11027394 [patent_doc_number] => 20160224350 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-08-04 [patent_title] => 'CONCURRENT MULTIPLE INSTRUCTION ISSUE OF NON-PIPELINED INSTRUCTIONS USING NON-PIPELINED OPERATION RESOURCES IN ANOTHER PROCESSING CORE' [patent_app_type] => utility [patent_app_number] => 15/093205 [patent_app_country] => US [patent_app_date] => 2016-04-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8661 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15093205 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/093205
Concurrent multiple instruction issued of non-pipelined instructions using non-pipelined operation resources in another processing core Apr 6, 2016 Issued
Array ( [id] => 11577527 [patent_doc_number] => 09632788 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-04-25 [patent_title] => 'Buffering instructions of a single branch, backwards short loop within a virtual loop buffer' [patent_app_type] => utility [patent_app_number] => 15/090749 [patent_app_country] => US [patent_app_date] => 2016-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4219 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 217 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15090749 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/090749
Buffering instructions of a single branch, backwards short loop within a virtual loop buffer Apr 4, 2016 Issued
Array ( [id] => 17288214 [patent_doc_number] => 11204764 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-12-21 [patent_title] => Processors, methods, systems, and instructions to Partition a source packed data into lanes [patent_app_type] => utility [patent_app_number] => 15/087231 [patent_app_country] => US [patent_app_date] => 2016-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 29 [patent_no_of_words] => 26876 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15087231 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/087231
Processors, methods, systems, and instructions to Partition a source packed data into lanes Mar 30, 2016 Issued
Array ( [id] => 11117021 [patent_doc_number] => 20160313995 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-10-27 [patent_title] => 'COMPUTER PROCESSOR WITH INDIRECT ONLY BRANCHING' [patent_app_type] => utility [patent_app_number] => 15/086752 [patent_app_country] => US [patent_app_date] => 2016-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 17969 [patent_no_of_claims] => 44 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15086752 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/086752
COMPUTER PROCESSOR WITH INDIRECT ONLY BRANCHING Mar 30, 2016 Abandoned
Array ( [id] => 11981954 [patent_doc_number] => 20170286108 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-10-05 [patent_title] => 'Processor Core, Processor And Method For Executing A Composite Scalar-Vector Very Lare Instruction Word (VLIW) Instruction' [patent_app_type] => utility [patent_app_number] => 15/086947 [patent_app_country] => US [patent_app_date] => 2016-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 6932 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15086947 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/086947
Executing a composite VLIW instruction having a scalar atom that indicates an iteration of execution Mar 30, 2016 Issued
Array ( [id] => 16833915 [patent_doc_number] => 11010166 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-05-18 [patent_title] => Arithmetic logic unit with normal and accelerated performance modes using differing numbers of computational circuits [patent_app_type] => utility [patent_app_number] => 15/087854 [patent_app_country] => US [patent_app_date] => 2016-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 31 [patent_no_of_words] => 26807 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 240 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15087854 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/087854
Arithmetic logic unit with normal and accelerated performance modes using differing numbers of computational circuits Mar 30, 2016 Issued
Array ( [id] => 18519788 [patent_doc_number] => 11709679 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-07-25 [patent_title] => Providing load address predictions using address prediction tables based on load path history in processor-based systems [patent_app_type] => utility [patent_app_number] => 15/087069 [patent_app_country] => US [patent_app_date] => 2016-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7955 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15087069 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/087069
Providing load address predictions using address prediction tables based on load path history in processor-based systems Mar 30, 2016 Issued
Array ( [id] => 10999197 [patent_doc_number] => 20160196144 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-07-07 [patent_title] => 'Sharing Program Interrupt Logic in a Multithreaded Processor' [patent_app_type] => utility [patent_app_number] => 15/082122 [patent_app_country] => US [patent_app_date] => 2016-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4776 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15082122 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/082122
Sharing program interrupt logic in a multithreaded processor Mar 27, 2016 Issued
Array ( [id] => 11086275 [patent_doc_number] => 20160283241 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-09-29 [patent_title] => 'PARALLEL DATA PROCESSING APPARATUS' [patent_app_type] => utility [patent_app_number] => 15/073573 [patent_app_country] => US [patent_app_date] => 2016-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 12773 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15073573 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/073573
PARALLEL DATA PROCESSING APPARATUS Mar 16, 2016 Abandoned
Array ( [id] => 15609277 [patent_doc_number] => 10585700 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-03-10 [patent_title] => Multi-phased and multi-threaded program execution based on SIMD ratio [patent_app_type] => utility [patent_app_number] => 15/056866 [patent_app_country] => US [patent_app_date] => 2016-02-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3053 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15056866 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/056866
Multi-phased and multi-threaded program execution based on SIMD ratio Feb 28, 2016 Issued
Array ( [id] => 10808492 [patent_doc_number] => 20160154650 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-06-02 [patent_title] => 'EFFICIENT USAGE OF A MULTI-LEVEL REGISTER FILE UTILIZING A REGISTER FILE BYPASS' [patent_app_type] => utility [patent_app_number] => 15/013018 [patent_app_country] => US [patent_app_date] => 2016-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 11841 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15013018 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/013018
Bypassing a higher level register file in a processor having a multi-level register file and a set of bypass registers Feb 1, 2016 Issued
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