Search

David J. Huisman

Examiner (ID: 10967, Phone: (571)272-4168 , Office: P/2183 )

Most Active Art Unit
2183
Art Unit(s)
2183
Total Applications
937
Issued Applications
493
Pending Applications
137
Abandoned Applications
337

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 11473800 [patent_doc_number] => 20170060583 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-03-02 [patent_title] => 'PROCESSOR AND METHOD OF HANDLING AN INSTRUCTION DATA THEREIN' [patent_app_type] => utility [patent_app_number] => 15/005553 [patent_app_country] => US [patent_app_date] => 2016-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6024 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15005553 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/005553
Handling Instruction Data and Shared resources in a Processor Having an Architecture Including a Pre-Execution Pipeline and a Resource and a Resource Tracker Circuit Based on Credit Availability Jan 24, 2016 Issued
Array ( [id] => 11708862 [patent_doc_number] => 20170177361 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-22 [patent_title] => 'APPARATUS AND METHOD FOR ACCELERATING GRAPH ANALYTICS' [patent_app_type] => utility [patent_app_number] => 14/978229 [patent_app_country] => US [patent_app_date] => 2015-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 17191 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14978229 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/978229
APPARATUS AND METHOD FOR ACCELERATING GRAPH ANALYTICS Dec 21, 2015 Abandoned
Array ( [id] => 11708837 [patent_doc_number] => 20170177336 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-22 [patent_title] => 'HARDWARE CANCELLATION MONITOR FOR FLOATING POINT OPERATIONS' [patent_app_type] => utility [patent_app_number] => 14/977821 [patent_app_country] => US [patent_app_date] => 2015-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 14822 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14977821 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/977821
HARDWARE CANCELLATION MONITOR FOR FLOATING POINT OPERATIONS Dec 21, 2015 Abandoned
Array ( [id] => 11708867 [patent_doc_number] => 20170177365 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-22 [patent_title] => 'TRANSACTION END PLUS COMMIT TO PERSISTENCE INSTRUCTIONS, PROCESSORS, METHODS, AND SYSTEMS' [patent_app_type] => utility [patent_app_number] => 14/979083 [patent_app_country] => US [patent_app_date] => 2015-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 23105 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14979083 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/979083
Transaction end plus commit to persistence instructions, processors, methods, and systems Dec 21, 2015 Issued
Array ( [id] => 17331390 [patent_doc_number] => 11221853 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-01-11 [patent_title] => Method of dispatching instruction data when a number of available resource credits meets a resource requirement [patent_app_type] => utility [patent_app_number] => 14/952241 [patent_app_country] => US [patent_app_date] => 2015-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 14 [patent_no_of_words] => 7744 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14952241 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/952241
Method of dispatching instruction data when a number of available resource credits meets a resource requirement Nov 24, 2015 Issued
Array ( [id] => 15198193 [patent_doc_number] => 10496592 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-12-03 [patent_title] => System and method to effectively overlap computation and reduction operation of nonblocking collective communication [patent_app_type] => utility [patent_app_number] => 14/949049 [patent_app_country] => US [patent_app_date] => 2015-11-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 19 [patent_no_of_words] => 10922 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 275 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14949049 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/949049
System and method to effectively overlap computation and reduction operation of nonblocking collective communication Nov 22, 2015 Issued
Array ( [id] => 11473808 [patent_doc_number] => 20170060591 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-03-02 [patent_title] => 'SYSTEM AND METHOD FOR MULTI-BRANCH SWITCHING' [patent_app_type] => utility [patent_app_number] => 14/949204 [patent_app_country] => US [patent_app_date] => 2015-11-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6245 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14949204 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/949204
SYSTEM AND METHOD FOR MULTI-BRANCH SWITCHING Nov 22, 2015 Abandoned
Array ( [id] => 11651445 [patent_doc_number] => 20170147346 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-05-25 [patent_title] => 'APPARATUS AND METHOD FOR MANAGING A BRANCH INFORMATION STORAGE' [patent_app_type] => utility [patent_app_number] => 14/947030 [patent_app_country] => US [patent_app_date] => 2015-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 11247 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14947030 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/947030
Apparatus and method for sharing branch information storage entries between threads that share an address translation regime Nov 19, 2015 Issued
Array ( [id] => 11658860 [patent_doc_number] => 09671856 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-06-06 [patent_title] => 'Apparatus and method for activating and shutting down enhanced pipeline stages and enhanced modules based on priority and performance requirements' [patent_app_type] => utility [patent_app_number] => 14/947823 [patent_app_country] => US [patent_app_date] => 2015-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7070 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 450 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14947823 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/947823
Apparatus and method for activating and shutting down enhanced pipeline stages and enhanced modules based on priority and performance requirements Nov 19, 2015 Issued
Array ( [id] => 11516245 [patent_doc_number] => 20170083319 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-03-23 [patent_title] => 'GENERATION AND USE OF BLOCK BRANCH METADATA' [patent_app_type] => utility [patent_app_number] => 14/948068 [patent_app_country] => US [patent_app_date] => 2015-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 17186 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14948068 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/948068
GENERATION AND USE OF BLOCK BRANCH METADATA Nov 19, 2015 Abandoned
Array ( [id] => 11606491 [patent_doc_number] => 20170123794 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-05-04 [patent_title] => 'TIGHTLY COUPLED PROCESSOR ARRAYS USING COARSE GRAINED RECONFIGURABLE ARCHITECTURE WITH ITERATION LEVEL COMMITS' [patent_app_type] => utility [patent_app_number] => 14/932629 [patent_app_country] => US [patent_app_date] => 2015-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 20648 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14932629 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/932629
Tightly coupled processor arrays using coarse grained reconfigurable architecture with iteration level commits Nov 3, 2015 Issued
Array ( [id] => 11606489 [patent_doc_number] => 20170123792 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-05-04 [patent_title] => 'Processors Supporting Endian Agnostic SIMD Instructions and Methods' [patent_app_type] => utility [patent_app_number] => 14/930740 [patent_app_country] => US [patent_app_date] => 2015-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 8114 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14930740 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/930740
Processors Supporting Endian Agnostic SIMD Instructions and Methods Nov 2, 2015 Abandoned
Array ( [id] => 11606497 [patent_doc_number] => 20170123799 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-05-04 [patent_title] => 'PERFORMING FOLDING OF IMMEDIATE DATA IN A PROCESSOR' [patent_app_type] => utility [patent_app_number] => 14/930761 [patent_app_country] => US [patent_app_date] => 2015-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 30 [patent_no_of_words] => 21276 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14930761 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/930761
PERFORMING FOLDING OF IMMEDIATE DATA IN A PROCESSOR Nov 2, 2015 Abandoned
Array ( [id] => 15231581 [patent_doc_number] => 10503512 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-12-10 [patent_title] => Context sensitive barriers with an implicit access ordering constraint for a victim context [patent_app_type] => utility [patent_app_number] => 14/930920 [patent_app_country] => US [patent_app_date] => 2015-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 7351 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 230 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14930920 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/930920
Context sensitive barriers with an implicit access ordering constraint for a victim context Nov 2, 2015 Issued
Array ( [id] => 10702247 [patent_doc_number] => 20160048395 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-02-18 [patent_title] => 'Branch Predictor for Wide Issue, Arbitrarily Aligned Fetch' [patent_app_type] => utility [patent_app_number] => 14/923947 [patent_app_country] => US [patent_app_date] => 2015-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6845 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14923947 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/923947
Branch Predictor for Wide Issue, Arbitrarily Aligned Fetch Oct 26, 2015 Abandoned
Array ( [id] => 10680320 [patent_doc_number] => 20160026465 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-01-28 [patent_title] => 'DATA PROCESSING APPARATUS AND METHOD' [patent_app_type] => utility [patent_app_number] => 14/878188 [patent_app_country] => US [patent_app_date] => 2015-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 18003 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14878188 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/878188
Apparatus and method including an instruction for performing a logical operation on a repeating data value generated based on data size and control parameter portions specified by the instruction Oct 7, 2015 Issued
Array ( [id] => 10801380 [patent_doc_number] => 20160147537 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-05-26 [patent_title] => 'Transitioning the Processor Core from Thread to Lane Mode and Enabling Data Transfer Between the Two Modes' [patent_app_type] => utility [patent_app_number] => 14/870367 [patent_app_country] => US [patent_app_date] => 2015-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7824 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14870367 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/870367
Transitioning the Processor Core from Thread to Lane Mode and Enabling Data Transfer Between the Two Modes Sep 29, 2015 Abandoned
Array ( [id] => 13679483 [patent_doc_number] => 20160378478 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-12-29 [patent_title] => INSTRUCTIONS TO COUNT CONTIGUOUS REGISTER ELEMENTS HAVING SPECIFIC VALUES [patent_app_type] => utility [patent_app_number] => 14/869853 [patent_app_country] => US [patent_app_date] => 2015-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12155 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14869853 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/869853
Instructions to count contiguous register elements having a specific value in a selected location Sep 28, 2015 Issued
Array ( [id] => 11509123 [patent_doc_number] => 09600283 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-03-21 [patent_title] => 'Single instruction for specifying a subset of registers to save prior to entering low-power mode, and for specifying a pointer to a function executed after exiting low-power mode' [patent_app_type] => utility [patent_app_number] => 14/854082 [patent_app_country] => US [patent_app_date] => 2015-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 11526 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14854082 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/854082
Single instruction for specifying a subset of registers to save prior to entering low-power mode, and for specifying a pointer to a function executed after exiting low-power mode Sep 14, 2015 Issued
Array ( [id] => 10739406 [patent_doc_number] => 20160085557 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-03-24 [patent_title] => 'PROCESSOR AND PROCESSING METHOD OF VECTOR INSTRUCTION' [patent_app_type] => utility [patent_app_number] => 14/840413 [patent_app_country] => US [patent_app_date] => 2015-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 8173 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14840413 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/840413
PROCESSOR AND PROCESSING METHOD OF VECTOR INSTRUCTION Aug 30, 2015 Abandoned
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