Search

David J. Huisman

Examiner (ID: 10967, Phone: (571)272-4168 , Office: P/2183 )

Most Active Art Unit
2183
Art Unit(s)
2183
Total Applications
937
Issued Applications
493
Pending Applications
137
Abandoned Applications
337

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 11473803 [patent_doc_number] => 20170060586 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-03-02 [patent_title] => 'LOAD STORE CIRCUIT WITH DEDICATED SINGLE OR DUAL BIT SHIFT CIRCUIT AND OPCODES FOR LOW POWER ACCELERATOR PROCESSOR' [patent_app_type] => utility [patent_app_number] => 14/840308 [patent_app_country] => US [patent_app_date] => 2015-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6720 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14840308 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/840308
Load store circuit with dedicated single or dual bit shift circuit and opcodes for low power accelerator processor Aug 30, 2015 Issued
Array ( [id] => 15386861 [patent_doc_number] => 10534615 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-01-14 [patent_title] => Combining instructions from different branches for execution in a single n-way VLIW processing element of a multithreaded processor [patent_app_type] => utility [patent_app_number] => 14/836086 [patent_app_country] => US [patent_app_date] => 2015-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4526 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14836086 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/836086
Combining instructions from different branches for execution in a single n-way VLIW processing element of a multithreaded processor Aug 25, 2015 Issued
Array ( [id] => 15638507 [patent_doc_number] => 10592247 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-03-17 [patent_title] => Arithmetic circuit and control method with full element permutation and element concatenate shift left [patent_app_type] => utility [patent_app_number] => 14/833602 [patent_app_country] => US [patent_app_date] => 2015-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 22 [patent_no_of_words] => 7227 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 338 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14833602 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/833602
Arithmetic circuit and control method with full element permutation and element concatenate shift left Aug 23, 2015 Issued
Array ( [id] => 11458876 [patent_doc_number] => 20170052782 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-02-23 [patent_title] => 'DELAYED ZERO-OVERHEAD LOOP INSTRUCTION' [patent_app_type] => utility [patent_app_number] => 14/831955 [patent_app_country] => US [patent_app_date] => 2015-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7222 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14831955 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/831955
DELAYED ZERO-OVERHEAD LOOP INSTRUCTION Aug 20, 2015 Abandoned
Array ( [id] => 11458970 [patent_doc_number] => 20170052876 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-02-23 [patent_title] => 'METHOD FOR OBSERVING SOFTWARE EXECUTION, DEBUG HOST AND DEBUG TARGET' [patent_app_type] => utility [patent_app_number] => 14/769812 [patent_app_country] => US [patent_app_date] => 2015-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7693 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14769812 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/769812
Observation by a debug host with memory model and timing offset calculation between instruction and data traces of software execution carried on in a debug target having a main memory and a cache arrangement Aug 17, 2015 Issued
Array ( [id] => 10470924 [patent_doc_number] => 20150355940 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-12-10 [patent_title] => 'IDLE TIME ACCUMULATION IN A MULTITHREADING COMPUTER SYSTEM' [patent_app_type] => utility [patent_app_number] => 14/828795 [patent_app_country] => US [patent_app_date] => 2015-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 12017 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14828795 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/828795
Method for executing a query instruction for idle time accumulation among cores in a multithreading computer system Aug 17, 2015 Issued
Array ( [id] => 10439221 [patent_doc_number] => 20150324233 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-11-12 [patent_title] => 'DATA STORAGE RESOURCE ALLOCATION USING BLACKLISTING OF RESOURCE REQUEST POOLS SUCH AS CATEGORIES OF DATA STORAGE REQUESTS' [patent_app_type] => utility [patent_app_number] => 14/804446 [patent_app_country] => US [patent_app_date] => 2015-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8853 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14804446 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/804446
Data storage resource allocation using blacklisting of data storage requests classified in the same category as a data storage request that is determined to fail if attempted Jul 20, 2015 Issued
Array ( [id] => 12046376 [patent_doc_number] => 09823979 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-11-21 [patent_title] => 'Updating a list of data storage requests if an abbreviated resource check determines that a request in the list would fail if attempted' [patent_app_type] => utility [patent_app_number] => 14/804376 [patent_app_country] => US [patent_app_date] => 2015-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 8846 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 237 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14804376 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/804376
Updating a list of data storage requests if an abbreviated resource check determines that a request in the list would fail if attempted Jul 20, 2015 Issued
Array ( [id] => 13679481 [patent_doc_number] => 20160378477 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-12-29 [patent_title] => INSTRUCTIONS TO COUNT CONTIGUOUS REGISTER ELEMENTS HAVING SPECIFIC VALUES [patent_app_type] => utility [patent_app_number] => 14/748550 [patent_app_country] => US [patent_app_date] => 2015-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12402 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14748550 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/748550
Instructions to count contiguous register elements having a specific value in a selected location Jun 23, 2015 Issued
Array ( [id] => 13679457 [patent_doc_number] => 20160378465 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-12-29 [patent_title] => EFFICIENT SPARSE ARRAY HANDLING IN A PROCESSOR [patent_app_type] => utility [patent_app_number] => 14/747182 [patent_app_country] => US [patent_app_date] => 2015-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 20646 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14747182 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/747182
EFFICIENT SPARSE ARRAY HANDLING IN A PROCESSOR Jun 22, 2015 Abandoned
Array ( [id] => 18519791 [patent_doc_number] => 11709682 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-07-25 [patent_title] => Replicating logic blocks to enable increased throughput with sequential enabling of input register blocks [patent_app_type] => utility [patent_app_number] => 14/745880 [patent_app_country] => US [patent_app_date] => 2015-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7526 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14745880 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/745880
Replicating logic blocks to enable increased throughput with sequential enabling of input register blocks Jun 21, 2015 Issued
Array ( [id] => 12571095 [patent_doc_number] => 10019283 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-07-10 [patent_title] => Predicting a context portion to move between a context buffer and registers based on context portions previously used by at least one other thread [patent_app_type] => utility [patent_app_number] => 14/746601 [patent_app_country] => US [patent_app_date] => 2015-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 6628 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14746601 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/746601
Predicting a context portion to move between a context buffer and registers based on context portions previously used by at least one other thread Jun 21, 2015 Issued
Array ( [id] => 15700951 [patent_doc_number] => 10606651 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-03-31 [patent_title] => Free form expression accelerator with thread length-based thread assignment to clustered soft processor cores that share a functional circuit [patent_app_type] => utility [patent_app_number] => 14/745385 [patent_app_country] => US [patent_app_date] => 2015-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 41 [patent_figures_cnt] => 51 [patent_no_of_words] => 23058 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 305 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14745385 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/745385
Free form expression accelerator with thread length-based thread assignment to clustered soft processor cores that share a functional circuit Jun 19, 2015 Issued
Array ( [id] => 11077951 [patent_doc_number] => 20160274915 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-09-22 [patent_title] => 'PROVIDING LOWER-OVERHEAD MANAGEMENT OF DATAFLOW EXECUTION OF LOOP INSTRUCTIONS BY OUT-OF-ORDER PROCESSORS (OOPs), AND RELATED CIRCUITS, METHODS, AND COMPUTER-READABLE MEDIA' [patent_app_type] => utility [patent_app_number] => 14/743198 [patent_app_country] => US [patent_app_date] => 2015-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 8978 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14743198 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/743198
PROVIDING LOWER-OVERHEAD MANAGEMENT OF DATAFLOW EXECUTION OF LOOP INSTRUCTIONS BY OUT-OF-ORDER PROCESSORS (OOPs), AND RELATED CIRCUITS, METHODS, AND COMPUTER-READABLE MEDIA Jun 17, 2015 Abandoned
Array ( [id] => 11672353 [patent_doc_number] => 20170161075 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-08 [patent_title] => 'INCREASING PROCESSOR INSTRUCTION WINDOW VIA SEPERATING INSTRUCTIONS ACCORDING TO CRITICALITY' [patent_app_type] => utility [patent_app_number] => 15/021442 [patent_app_country] => US [patent_app_date] => 2015-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 14946 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15021442 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/021442
INCREASING PROCESSOR INSTRUCTION WINDOW VIA SEPERATING INSTRUCTIONS ACCORDING TO CRITICALITY May 31, 2015 Abandoned
Array ( [id] => 13226539 [patent_doc_number] => 10127045 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-11-13 [patent_title] => Machine tool controller including a multi-core processor for dividing a large-sized program into portions stored in different lockable instruction caches [patent_app_type] => utility [patent_app_number] => 14/669322 [patent_app_country] => US [patent_app_date] => 2015-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 16 [patent_no_of_words] => 5181 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 301 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14669322 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/669322
Machine tool controller including a multi-core processor for dividing a large-sized program into portions stored in different lockable instruction caches Mar 25, 2015 Issued
Array ( [id] => 11086266 [patent_doc_number] => 20160283233 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-09-29 [patent_title] => 'COMPUTER SYSTEMS AND METHODS FOR CONTEXT SWITCHING' [patent_app_type] => utility [patent_app_number] => 14/667229 [patent_app_country] => US [patent_app_date] => 2015-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4093 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14667229 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/667229
COMPUTER SYSTEMS AND METHODS FOR CONTEXT SWITCHING Mar 23, 2015 Abandoned
Array ( [id] => 12290505 [patent_doc_number] => 09933841 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-04-03 [patent_title] => Reuse of results of back-to-back micro-operations [patent_app_type] => utility [patent_app_number] => 14/664241 [patent_app_country] => US [patent_app_date] => 2015-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 18 [patent_no_of_words] => 13310 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 221 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14664241 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/664241
Reuse of results of back-to-back micro-operations Mar 19, 2015 Issued
Array ( [id] => 15284529 [patent_doc_number] => 10514928 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-12-24 [patent_title] => Preventing duplicate execution by sharing a result between different processing lanes assigned micro-operations that generate the same result [patent_app_type] => utility [patent_app_number] => 14/663858 [patent_app_country] => US [patent_app_date] => 2015-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 18 [patent_no_of_words] => 13891 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14663858 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/663858
Preventing duplicate execution by sharing a result between different processing lanes assigned micro-operations that generate the same result Mar 19, 2015 Issued
Array ( [id] => 11078079 [patent_doc_number] => 20160275043 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-09-22 [patent_title] => 'ENERGY AND AREA OPTIMIZED HETEROGENEOUS MULTIPROCESSOR FOR CASCADE CLASSIFIERS' [patent_app_type] => utility [patent_app_number] => 14/662089 [patent_app_country] => US [patent_app_date] => 2015-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 12844 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14662089 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/662089
Heterogeneous multiprocessor including scalar and SIMD processors in a ratio defined by execution time and consumed die area Mar 17, 2015 Issued
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