Search

David J. Huisman

Examiner (ID: 10967, Phone: (571)272-4168 , Office: P/2183 )

Most Active Art Unit
2183
Art Unit(s)
2183
Total Applications
937
Issued Applications
493
Pending Applications
137
Abandoned Applications
337

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 20145584 [patent_doc_number] => 12379926 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-08-05 [patent_title] => Image processing apparatus with multibank registers for storing source, destination, and setting information for operational circuits [patent_app_type] => utility [patent_app_number] => 18/350022 [patent_app_country] => US [patent_app_date] => 2023-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2424 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 540 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18350022 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/350022
Image processing apparatus with multibank registers for storing source, destination, and setting information for operational circuits Jul 10, 2023 Issued
Array ( [id] => 18741732 [patent_doc_number] => 20230350713 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-02 [patent_title] => PARALLEL PROCESSING ARCHITECTURE WITH COUNTDOWN TAGGING [patent_app_type] => utility [patent_app_number] => 18/220331 [patent_app_country] => US [patent_app_date] => 2023-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16199 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18220331 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/220331
PARALLEL PROCESSING ARCHITECTURE WITH COUNTDOWN TAGGING Jul 10, 2023 Pending
Array ( [id] => 18973891 [patent_doc_number] => 20240053983 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-15 [patent_title] => Performance Optimized Task Duplication and Migration [patent_app_type] => utility [patent_app_number] => 18/220536 [patent_app_country] => US [patent_app_date] => 2023-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6805 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18220536 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/220536
Performance Optimized Task Duplication and Migration Jul 10, 2023 Pending
Array ( [id] => 19685985 [patent_doc_number] => 20250004530 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-02 [patent_title] => LIMITED BIT TOGGLING FOR DATA BUS INVERSION [patent_app_type] => utility [patent_app_number] => 18/345940 [patent_app_country] => US [patent_app_date] => 2023-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4503 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18345940 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/345940
LIMITED BIT TOGGLING FOR DATA BUS INVERSION Jun 29, 2023 Pending
Array ( [id] => 18727859 [patent_doc_number] => 20230342152 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-26 [patent_title] => PARALLEL PROCESSING ARCHITECTURE WITH SPLIT CONTROL WORD CACHES [patent_app_type] => utility [patent_app_number] => 18/215866 [patent_app_country] => US [patent_app_date] => 2023-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19032 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 207 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18215866 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/215866
PARALLEL PROCESSING ARCHITECTURE WITH SPLIT CONTROL WORD CACHES Jun 28, 2023 Pending
Array ( [id] => 18846930 [patent_doc_number] => 20230409334 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-21 [patent_title] => PROVIDING CODE SECTIONS FOR MATRIX OF ARITHMETIC LOGIC UNITS IN A PROCESSOR [patent_app_type] => utility [patent_app_number] => 18/214385 [patent_app_country] => US [patent_app_date] => 2023-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 34684 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18214385 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/214385
PROVIDING CODE SECTIONS FOR MATRIX OF ARITHMETIC LOGIC UNITS IN A PROCESSOR Jun 25, 2023 Pending
Array ( [id] => 18711377 [patent_doc_number] => 20230334006 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-19 [patent_title] => COMPUTE NEAR MEMORY CONVOLUTION ACCELERATOR [patent_app_type] => utility [patent_app_number] => 18/212079 [patent_app_country] => US [patent_app_date] => 2023-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10165 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 204 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18212079 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/212079
COMPUTE NEAR MEMORY CONVOLUTION ACCELERATOR Jun 19, 2023 Pending
Array ( [id] => 18694777 [patent_doc_number] => 20230325195 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-12 [patent_title] => REPLICATING LOGIC BLOCKS TO ENABLE INCREASED THROUGHPUT WITH SEQUENTIAL ENABLING OF INPUT REGISTER BLOCKS [patent_app_type] => utility [patent_app_number] => 18/207056 [patent_app_country] => US [patent_app_date] => 2023-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7583 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18207056 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/207056
REPLICATING LOGIC BLOCKS TO ENABLE INCREASED THROUGHPUT WITH SEQUENTIAL ENABLING OF INPUT REGISTER BLOCKS Jun 6, 2023 Pending
Array ( [id] => 18614277 [patent_doc_number] => 20230281014 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-07 [patent_title] => PARALLEL PROCESSING OF MULTIPLE LOOPS WITH LOADS AND STORES [patent_app_type] => utility [patent_app_number] => 18/195407 [patent_app_country] => US [patent_app_date] => 2023-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19987 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -24 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18195407 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/195407
PARALLEL PROCESSING OF MULTIPLE LOOPS WITH LOADS AND STORES May 9, 2023 Pending
Array ( [id] => 18711223 [patent_doc_number] => 20230333852 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-19 [patent_title] => DATAFLOW-BASED GENERAL-PURPOSE PROCESSOR ARCHITECTURES [patent_app_type] => utility [patent_app_number] => 18/301776 [patent_app_country] => US [patent_app_date] => 2023-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11537 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18301776 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/301776
DATAFLOW-BASED GENERAL-PURPOSE PROCESSOR ARCHITECTURES Apr 16, 2023 Pending
Array ( [id] => 19303549 [patent_doc_number] => 20240232129 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-11 [patent_title] => Programmable Compute Architecture [patent_app_type] => utility [patent_app_number] => 18/297296 [patent_app_country] => US [patent_app_date] => 2023-04-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3710 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18297296 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/297296
Programmable Compute Architecture Apr 6, 2023 Abandoned
Array ( [id] => 18677825 [patent_doc_number] => 20230315472 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-05 [patent_title] => SYSTEM FOR MANAGING A GROUP OF ROTATING REGISTERS DEFINED ARBITRARILY IN A PROCESSOR REGISTER FILE [patent_app_type] => utility [patent_app_number] => 18/192947 [patent_app_country] => US [patent_app_date] => 2023-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4177 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -4 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18192947 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/192947
SYSTEM FOR MANAGING A GROUP OF ROTATING REGISTERS DEFINED ARBITRARILY IN A PROCESSOR REGISTER FILE Mar 29, 2023 Pending
Array ( [id] => 18499189 [patent_doc_number] => 20230221931 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-07-13 [patent_title] => AUTONOMOUS COMPUTE ELEMENT OPERATION USING BUFFERS [patent_app_type] => utility [patent_app_number] => 18/124115 [patent_app_country] => US [patent_app_date] => 2023-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17194 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18124115 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/124115
AUTONOMOUS COMPUTE ELEMENT OPERATION USING BUFFERS Mar 20, 2023 Pending
Array ( [id] => 20110049 [patent_doc_number] => 12360770 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-15 [patent_title] => System and method for providing lock-free self-service queue [patent_app_type] => utility [patent_app_number] => 18/123599 [patent_app_country] => US [patent_app_date] => 2023-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 6189 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 326 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18123599 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/123599
System and method for providing lock-free self-service queue Mar 19, 2023 Issued
Array ( [id] => 19451033 [patent_doc_number] => 20240311163 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-19 [patent_title] => HARDWARE-DRIVEN CALL STACK ATTRIBUTION [patent_app_type] => utility [patent_app_number] => 18/122832 [patent_app_country] => US [patent_app_date] => 2023-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10654 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18122832 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/122832
HARDWARE-DRIVEN CALL STACK ATTRIBUTION Mar 16, 2023 Pending
Array ( [id] => 18471256 [patent_doc_number] => 20230205542 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-29 [patent_title] => ELECTRONIC APPARATUS AND METHOD FOR REDUCING NUMBER OF COMMANDS [patent_app_type] => utility [patent_app_number] => 18/176496 [patent_app_country] => US [patent_app_date] => 2023-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6466 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -2 [patent_words_short_claim] => 259 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18176496 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/176496
ELECTRONIC APPARATUS AND METHOD FOR REDUCING NUMBER OF COMMANDS Feb 28, 2023 Pending
Array ( [id] => 18471255 [patent_doc_number] => 20230205541 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-29 [patent_title] => ELECTRONIC APPARATUS AND METHOD FOR REDUCING NUMBER OF COMMANDS [patent_app_type] => utility [patent_app_number] => 18/176493 [patent_app_country] => US [patent_app_date] => 2023-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6466 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -4 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18176493 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/176493
ELECTRONIC APPARATUS AND METHOD FOR REDUCING NUMBER OF COMMANDS Feb 28, 2023 Pending
Array ( [id] => 19267625 [patent_doc_number] => 20240211328 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-27 [patent_title] => RESILIENT POST-PROCESSING ARCHITECTURE FOR ABNORMAL PROCESS TERMINATION [patent_app_type] => utility [patent_app_number] => 18/115462 [patent_app_country] => US [patent_app_date] => 2023-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5583 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18115462 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/115462
RESILIENT POST-PROCESSING ARCHITECTURE FOR ABNORMAL PROCESS TERMINATION Feb 27, 2023 Pending
Array ( [id] => 18499215 [patent_doc_number] => 20230221959 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-07-13 [patent_title] => INSTRUCTION PACKING SCHEME FOR VLIW CPU ARCHITECTURE [patent_app_type] => utility [patent_app_number] => 18/174715 [patent_app_country] => US [patent_app_date] => 2023-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3647 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18174715 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/174715
INSTRUCTION PACKING SCHEME FOR VLIW CPU ARCHITECTURE Feb 26, 2023 Pending
Array ( [id] => 18454226 [patent_doc_number] => 20230195506 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-22 [patent_title] => SYSTEMS AND METHODS FOR PROCESSING ATOMIC COMMANDS [patent_app_type] => utility [patent_app_number] => 18/110605 [patent_app_country] => US [patent_app_date] => 2023-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 50452 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18110605 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/110605
SYSTEMS AND METHODS FOR PROCESSING ATOMIC COMMANDS Feb 15, 2023 Pending
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