Search

David J. Huisman

Examiner (ID: 4847, Phone: (571)272-4168 , Office: P/2183 )

Most Active Art Unit
2183
Art Unit(s)
2183
Total Applications
930
Issued Applications
493
Pending Applications
141
Abandoned Applications
335

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18279600 [patent_doc_number] => 20230095072 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-30 [patent_title] => Coprocessor Register Renaming [patent_app_type] => utility [patent_app_number] => 17/644016 [patent_app_country] => US [patent_app_date] => 2021-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13397 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17644016 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/644016
Coprocessor register renaming using registers associated with an inactive context to store results from an active context Dec 12, 2021 Issued
Array ( [id] => 19093034 [patent_doc_number] => 11954495 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2024-04-09 [patent_title] => Database acceleration with coprocessor subsystem for offloading tuple filtering [patent_app_type] => utility [patent_app_number] => 17/643777 [patent_app_country] => US [patent_app_date] => 2021-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 12344 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17643777 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/643777
Database acceleration with coprocessor subsystem for offloading tuple filtering Dec 9, 2021 Issued
Array ( [id] => 18703230 [patent_doc_number] => 11789740 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-10-17 [patent_title] => Performing branch predictor training using probabilistic counter updates in a processor [patent_app_type] => utility [patent_app_number] => 17/535359 [patent_app_country] => US [patent_app_date] => 2021-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 8936 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 203 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17535359 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/535359
Performing branch predictor training using probabilistic counter updates in a processor Nov 23, 2021 Issued
Array ( [id] => 17462354 [patent_doc_number] => 20220075659 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-10 [patent_title] => RUNTIME CONFIGURABLE REGISTER FILES FOR ARTIFICIAL INTELLIGENCE WORKLOADS [patent_app_type] => utility [patent_app_number] => 17/530156 [patent_app_country] => US [patent_app_date] => 2021-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 20134 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -24 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17530156 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/530156
RUNTIME CONFIGURABLE REGISTER FILES FOR ARTIFICIAL INTELLIGENCE WORKLOADS Nov 17, 2021 Pending
Array ( [id] => 19934051 [patent_doc_number] => 12307256 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2025-05-20 [patent_title] => Livelock detection and resolution using oldest operation tracking [patent_app_type] => utility [patent_app_number] => 17/526939 [patent_app_country] => US [patent_app_date] => 2021-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 8215 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17526939 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/526939
Livelock detection and resolution using oldest operation tracking Nov 14, 2021 Issued
Array ( [id] => 17629293 [patent_doc_number] => 20220164308 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-26 [patent_title] => SYSTOLIC ARRAY PROCESSOR AND OPERATING METHOD OF SYSTOLIC ARRAY PROCESSOR [patent_app_type] => utility [patent_app_number] => 17/523615 [patent_app_country] => US [patent_app_date] => 2021-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7886 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17523615 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/523615
SYSTOLIC ARRAY PROCESSOR AND OPERATING METHOD OF SYSTOLIC ARRAY PROCESSOR Nov 9, 2021 Abandoned
Array ( [id] => 17415613 [patent_doc_number] => 20220050517 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-02-17 [patent_title] => HARDWARE PROCESSORS AND METHODS FOR EXTENDED MICROCODE PATCHING [patent_app_type] => utility [patent_app_number] => 17/512119 [patent_app_country] => US [patent_app_date] => 2021-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 29373 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -27 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17512119 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/512119
HARDWARE PROCESSORS AND METHODS FOR EXTENDED MICROCODE PATCHING Oct 26, 2021 Pending
Array ( [id] => 17613804 [patent_doc_number] => 20220156084 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-19 [patent_title] => PROCESSOR ARCHITECTURE WITH MICRO-THREADING CONTROL BY HARDWARE-ACCELERATED KERNEL THREAD [patent_app_type] => utility [patent_app_number] => 17/451161 [patent_app_country] => US [patent_app_date] => 2021-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15305 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -26 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17451161 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/451161
Processor architecture with micro-threading control by hardware-accelerated kernel thread Oct 17, 2021 Issued
Array ( [id] => 17659190 [patent_doc_number] => 20220179655 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-09 [patent_title] => SYSTEMS AND METHODS FOR REDUCING REGISTER BANK CONFLICTS BASED ON SOFTWARE HINT AND HARDWARE THREAD SWITCH [patent_app_type] => utility [patent_app_number] => 17/502492 [patent_app_country] => US [patent_app_date] => 2021-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18292 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17502492 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/502492
SYSTEMS AND METHODS FOR REDUCING REGISTER BANK CONFLICTS BASED ON SOFTWARE HINT AND HARDWARE THREAD SWITCH Oct 14, 2021 Pending
Array ( [id] => 17462435 [patent_doc_number] => 20220075740 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-10 [patent_title] => PARALLEL PROCESSING ARCHITECTURE WITH BACKGROUND LOADS [patent_app_type] => utility [patent_app_number] => 17/500990 [patent_app_country] => US [patent_app_date] => 2021-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11203 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -23 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17500990 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/500990
PARALLEL PROCESSING ARCHITECTURE WITH BACKGROUND LOADS Oct 13, 2021 Pending
Array ( [id] => 17565126 [patent_doc_number] => 20220129275 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-04-28 [patent_title] => CIRCULAR QUEUE MANAGEMENT WITH SPLIT INDEXES [patent_app_type] => utility [patent_app_number] => 17/500851 [patent_app_country] => US [patent_app_date] => 2021-10-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17677 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -27 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17500851 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/500851
Circular queue management with split indexes Oct 12, 2021 Issued
Array ( [id] => 18281918 [patent_doc_number] => 20230097390 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-30 [patent_title] => TIGHTLY-COUPLED SLICE TARGET FILE DATA [patent_app_type] => utility [patent_app_number] => 17/489754 [patent_app_country] => US [patent_app_date] => 2021-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6237 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17489754 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/489754
TIGHTLY-COUPLED SLICE TARGET FILE DATA Sep 28, 2021 Pending
Array ( [id] => 18285221 [patent_doc_number] => 20230100693 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-30 [patent_title] => PREDICTION OF NEXT TAKEN BRANCHES IN A PROCESSOR [patent_app_type] => utility [patent_app_number] => 17/448795 [patent_app_country] => US [patent_app_date] => 2021-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 29925 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17448795 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/448795
PREDICTION OF NEXT TAKEN BRANCHES IN A PROCESSOR Sep 23, 2021 Abandoned
Array ( [id] => 17535526 [patent_doc_number] => 20220114135 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-04-14 [patent_title] => COMPUTER ARCHITECTURE FOR ARTIFICIAL INTELLIGENCE AND RECONFIGURABLE HARDWARE [patent_app_type] => utility [patent_app_number] => 17/481285 [patent_app_country] => US [patent_app_date] => 2021-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3202 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 38 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17481285 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/481285
COMPUTER ARCHITECTURE FOR ARTIFICIAL INTELLIGENCE AND RECONFIGURABLE HARDWARE Sep 20, 2021 Pending
Array ( [id] => 18268107 [patent_doc_number] => 20230089349 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-23 [patent_title] => Computer Architecture with Register Name Addressing and Dynamic Load Size Adjustment [patent_app_type] => utility [patent_app_number] => 17/480879 [patent_app_country] => US [patent_app_date] => 2021-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9917 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -25 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17480879 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/480879
Computer Architecture with Register Name Addressing and Dynamic Load Size Adjustment Sep 20, 2021 Pending
Array ( [id] => 17962087 [patent_doc_number] => 20220342668 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-27 [patent_title] => System of Multiple Stacks in a Processor Devoid of an Effective Address Generator [patent_app_type] => utility [patent_app_number] => 17/468574 [patent_app_country] => US [patent_app_date] => 2021-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9233 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17468574 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/468574
System of Multiple Stacks in a Processor Devoid of an Effective Address Generator Sep 6, 2021 Pending
Array ( [id] => 17462322 [patent_doc_number] => 20220075627 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-10 [patent_title] => HIGHLY PARALLEL PROCESSING ARCHITECTURE WITH SHALLOW PIPELINE [patent_app_type] => utility [patent_app_number] => 17/465949 [patent_app_country] => US [patent_app_date] => 2021-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11913 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -23 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17465949 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/465949
HIGHLY PARALLEL PROCESSING ARCHITECTURE WITH SHALLOW PIPELINE Sep 2, 2021 Pending
Array ( [id] => 19719363 [patent_doc_number] => 12204902 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-01-21 [patent_title] => Routing instruction results to a register block of a subdivided register file based on register block utilization rate [patent_app_type] => utility [patent_app_number] => 17/464227 [patent_app_country] => US [patent_app_date] => 2021-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 13324 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 228 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17464227 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/464227
Routing instruction results to a register block of a subdivided register file based on register block utilization rate Aug 31, 2021 Issued
Array ( [id] => 18239794 [patent_doc_number] => 20230072105 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-09 [patent_title] => BFLOAT16 COMPARISON INSTRUCTIONS [patent_app_type] => utility [patent_app_number] => 17/463410 [patent_app_country] => US [patent_app_date] => 2021-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16494 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17463410 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/463410
BFLOAT16 COMPARISON INSTRUCTIONS Aug 30, 2021 Abandoned
Array ( [id] => 18211360 [patent_doc_number] => 20230057623 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-02-23 [patent_title] => ISSUE, EXECUTION, AND BACKEND DRIVEN FRONTEND TRANSLATION CONTROL FOR PERFORMANT AND SECURE DATA-SPACE GUIDED MICRO-SEQUENCING [patent_app_type] => utility [patent_app_number] => 17/409062 [patent_app_country] => US [patent_app_date] => 2021-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14445 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17409062 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/409062
ISSUE, EXECUTION, AND BACKEND DRIVEN FRONTEND TRANSLATION CONTROL FOR PERFORMANT AND SECURE DATA-SPACE GUIDED MICRO-SEQUENCING Aug 22, 2021 Pending
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