| Application number | Title of the application | Filing Date | Status |
|---|
Array
(
[id] => 17962087
[patent_doc_number] => 20220342668
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-10-27
[patent_title] => System of Multiple Stacks in a Processor Devoid of an Effective Address Generator
[patent_app_type] => utility
[patent_app_number] => 17/468574
[patent_app_country] => US
[patent_app_date] => 2021-09-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9233
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -20
[patent_words_short_claim] => 97
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17468574
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/468574 | System of Multiple Stacks in a Processor Devoid of an Effective Address Generator | Sep 6, 2021 | Pending |
Array
(
[id] => 17462322
[patent_doc_number] => 20220075627
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-03-10
[patent_title] => HIGHLY PARALLEL PROCESSING ARCHITECTURE WITH SHALLOW PIPELINE
[patent_app_type] => utility
[patent_app_number] => 17/465949
[patent_app_country] => US
[patent_app_date] => 2021-09-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 11913
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -23
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17465949
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/465949 | HIGHLY PARALLEL PROCESSING ARCHITECTURE WITH SHALLOW PIPELINE | Sep 2, 2021 | Pending |
Array
(
[id] => 19719363
[patent_doc_number] => 12204902
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-01-21
[patent_title] => Routing instruction results to a register block of a subdivided register file based on register block utilization rate
[patent_app_type] => utility
[patent_app_number] => 17/464227
[patent_app_country] => US
[patent_app_date] => 2021-09-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 9
[patent_no_of_words] => 13324
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 228
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17464227
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/464227 | Routing instruction results to a register block of a subdivided register file based on register block utilization rate | Aug 31, 2021 | Issued |
Array
(
[id] => 18239794
[patent_doc_number] => 20230072105
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-03-09
[patent_title] => BFLOAT16 COMPARISON INSTRUCTIONS
[patent_app_type] => utility
[patent_app_number] => 17/463410
[patent_app_country] => US
[patent_app_date] => 2021-08-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 16494
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -19
[patent_words_short_claim] => 97
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17463410
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/463410 | BFLOAT16 COMPARISON INSTRUCTIONS | Aug 30, 2021 | Abandoned |
Array
(
[id] => 18211360
[patent_doc_number] => 20230057623
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-02-23
[patent_title] => ISSUE, EXECUTION, AND BACKEND DRIVEN FRONTEND TRANSLATION CONTROL FOR PERFORMANT AND SECURE DATA-SPACE GUIDED MICRO-SEQUENCING
[patent_app_type] => utility
[patent_app_number] => 17/409062
[patent_app_country] => US
[patent_app_date] => 2021-08-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 14445
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -22
[patent_words_short_claim] => 62
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17409062
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/409062 | ISSUE, EXECUTION, AND BACKEND DRIVEN FRONTEND TRANSLATION CONTROL FOR PERFORMANT AND SECURE DATA-SPACE GUIDED MICRO-SEQUENCING | Aug 22, 2021 | Abandoned |
Array
(
[id] => 18198336
[patent_doc_number] => 20230051855
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-02-16
[patent_title] => CALL AND RETURN INSTRUCTIONS FOR CONFIGURABLE REGISTER CONTEXT SAVE AND RESTORE
[patent_app_type] => utility
[patent_app_number] => 17/401718
[patent_app_country] => US
[patent_app_date] => 2021-08-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6311
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -3
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17401718
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/401718 | Call and return instructions for saving and restoring different sets of context registers mapped to different call opcodes | Aug 12, 2021 | Issued |
Array
(
[id] => 18164146
[patent_doc_number] => 20230030741
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-02-02
[patent_title] => EFFICIENT COMPRESSED VERBATIM COPY
[patent_app_type] => utility
[patent_app_number] => 17/390661
[patent_app_country] => US
[patent_app_date] => 2021-07-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 45540
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 80
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17390661
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/390661 | EFFICIENT COMPRESSED VERBATIM COPY | Jul 29, 2021 | Abandoned |
Array
(
[id] => 18196864
[patent_doc_number] => 20230050383
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-02-16
[patent_title] => NON-BLOCKING EXTERNAL DEVICE CALL
[patent_app_type] => utility
[patent_app_number] => 17/386985
[patent_app_country] => US
[patent_app_date] => 2021-07-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 21602
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -22
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17386985
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/386985 | Counter for preventing completion of a thread including a non-blocking external device call with no-return indication | Jul 27, 2021 | Issued |
Array
(
[id] => 20344809
[patent_doc_number] => 12468540
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-11-11
[patent_title] => Technologies for prediction-based register renaming
[patent_app_type] => utility
[patent_app_number] => 18/017792
[patent_app_country] => US
[patent_app_date] => 2021-07-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 2450
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 257
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18017792
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/017792 | Technologies for prediction-based register renaming | Jul 22, 2021 | Issued |
Array
(
[id] => 18079492
[patent_doc_number] => 20220405104
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-12-22
[patent_title] => CROSS PLATFORM AND PLATFORM AGNOSTIC ACCELERATOR REMOTING SERVICE
[patent_app_type] => utility
[patent_app_number] => 17/377893
[patent_app_country] => US
[patent_app_date] => 2021-07-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10099
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 148
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17377893
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/377893 | CROSS PLATFORM AND PLATFORM AGNOSTIC ACCELERATOR REMOTING SERVICE | Jul 15, 2021 | Pending |
Array
(
[id] => 18606637
[patent_doc_number] => 11748101
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-09-05
[patent_title] => Handling of single-copy-atomic load/store instruction with a memory access request shared by micro-operations
[patent_app_type] => utility
[patent_app_number] => 17/374149
[patent_app_country] => US
[patent_app_date] => 2021-07-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 10
[patent_no_of_words] => 14392
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 394
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17374149
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/374149 | Handling of single-copy-atomic load/store instruction with a memory access request shared by micro-operations | Jul 12, 2021 | Issued |
Array
(
[id] => 18553851
[patent_doc_number] => 20230251863
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-08-10
[patent_title] => MULTI-BIT REGISTER, CHIP, AND COMPUTING APPARATUS
[patent_app_type] => utility
[patent_app_number] => 18/005281
[patent_app_country] => US
[patent_app_date] => 2021-07-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4281
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -9
[patent_words_short_claim] => 80
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18005281
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/005281 | MULTI-BIT REGISTER, CHIP, AND COMPUTING APPARATUS | Jul 6, 2021 | Pending |
Array
(
[id] => 17261038
[patent_doc_number] => 20210374023
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-12-02
[patent_title] => FLEXIBLE INTERFACE
[patent_app_type] => utility
[patent_app_number] => 17/368450
[patent_app_country] => US
[patent_app_date] => 2021-07-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6149
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -21
[patent_words_short_claim] => 98
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17368450
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/368450 | FLEXIBLE INTERFACE | Jul 5, 2021 | Pending |
Array
(
[id] => 18095513
[patent_doc_number] => 20220413854
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-12-29
[patent_title] => 64-BIT TWO-DIMENSIONAL BLOCK LOAD WITH TRANSPOSE
[patent_app_type] => utility
[patent_app_number] => 17/358859
[patent_app_country] => US
[patent_app_date] => 2021-06-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 47188
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -21
[patent_words_short_claim] => 128
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17358859
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/358859 | 64-BIT TWO-DIMENSIONAL BLOCK LOAD WITH TRANSPOSE | Jun 24, 2021 | Pending |
Array
(
[id] => 20647286
[patent_doc_number] => 12602229
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2026-04-14
[patent_title] => Neural network accelerator for operating a consumer pipeline stage using a start flag set by a producer pipeline stage
[patent_app_type] => utility
[patent_app_number] => 17/351408
[patent_app_country] => US
[patent_app_date] => 2021-06-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 22675
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 97
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17351408
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/351408 | Neural network accelerator for operating a consumer pipeline stage using a start flag set by a producer pipeline stage | Jun 17, 2021 | Issued |
Array
(
[id] => 17230660
[patent_doc_number] => 20210357217
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-11-18
[patent_title] => SYSTEMS AND METHODS FOR EXECUTING A FUSED MULTIPLY-ADD INSTRUCTION FOR COMPLEX NUMBERS
[patent_app_type] => utility
[patent_app_number] => 17/335942
[patent_app_country] => US
[patent_app_date] => 2021-06-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 20014
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -21
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17335942
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/335942 | SYSTEMS AND METHODS FOR EXECUTING A FUSED MULTIPLY-ADD INSTRUCTION FOR COMPLEX NUMBERS | May 31, 2021 | Abandoned |
Array
(
[id] => 17613801
[patent_doc_number] => 20220156081
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-05-19
[patent_title] => PROCESSING-IN-MEMORY AND METHOD OF OUTPUTTING INSTRUCTION USING PROCESSING-IN-MEMORY
[patent_app_type] => utility
[patent_app_number] => 17/323171
[patent_app_country] => US
[patent_app_date] => 2021-05-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4764
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -13
[patent_words_short_claim] => 84
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17323171
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/323171 | Processor-in-memory storing a lookup table for providing an instruction in response to an API call instruction | May 17, 2021 | Issued |
Array
(
[id] => 19581693
[patent_doc_number] => 12147811
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-11-19
[patent_title] => Warp scheduling method for adjusting number of schedulable warps based on load/store unit stall cycle proportion
[patent_app_type] => utility
[patent_app_number] => 17/227422
[patent_app_country] => US
[patent_app_date] => 2021-04-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 7
[patent_no_of_words] => 6877
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 224
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17227422
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/227422 | Warp scheduling method for adjusting number of schedulable warps based on load/store unit stall cycle proportion | Apr 11, 2021 | Issued |
Array
(
[id] => 17899228
[patent_doc_number] => 20220308890
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-09-29
[patent_title] => MULTI-PROCESSING UNIT INTERCONNECTED ACCELERATOR SYSTEMS AND CONFIGURATION TECHNIQUES
[patent_app_type] => utility
[patent_app_number] => 17/216189
[patent_app_country] => US
[patent_app_date] => 2021-03-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4364
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 53
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17216189
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/216189 | MULTI-PROCESSING UNIT INTERCONNECTED ACCELERATOR SYSTEMS AND CONFIGURATION TECHNIQUES | Mar 28, 2021 | Pending |
Array
(
[id] => 18839386
[patent_doc_number] => 11847460
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-12-19
[patent_title] => Adaptive load coalescing for spatially proximate load requests based on predicted load request coalescence based on handling of previous load requests
[patent_app_type] => utility
[patent_app_number] => 17/211062
[patent_app_country] => US
[patent_app_date] => 2021-03-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 9
[patent_no_of_words] => 8303
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 278
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17211062
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/211062 | Adaptive load coalescing for spatially proximate load requests based on predicted load request coalescence based on handling of previous load requests | Mar 23, 2021 | Issued |