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David J. Huisman

Examiner (ID: 4847, Phone: (571)272-4168 , Office: P/2183 )

Most Active Art Unit
2183
Art Unit(s)
2183
Total Applications
930
Issued Applications
493
Pending Applications
141
Abandoned Applications
335

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16849580 [patent_doc_number] => 20210150325 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-05-20 [patent_title] => DATA PROCESSING METHOD AND APPARATUS, AND RELATED PRODUCT [patent_app_type] => utility [patent_app_number] => 17/137245 [patent_app_country] => US [patent_app_date] => 2020-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11550 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17137245 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/137245
DATA PROCESSING METHOD AND APPARATUS, AND RELATED PRODUCT Dec 28, 2020 Pending
Array ( [id] => 17706787 [patent_doc_number] => 20220206793 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-30 [patent_title] => METHODS, SYSTEMS, AND APPARATUSES FOR A SCALABLE RESERVATION STATION IMPLEMENTING A SINGLE UNIFIED SPECULATION STATE PROPAGATION AND EXECUTION WAKEUP MATRIX CIRCUIT IN A PROCESSOR [patent_app_type] => utility [patent_app_number] => 17/134154 [patent_app_country] => US [patent_app_date] => 2020-12-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 21486 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17134154 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/134154
METHODS, SYSTEMS, AND APPARATUSES FOR A SCALABLE RESERVATION STATION IMPLEMENTING A SINGLE UNIFIED SPECULATION STATE PROPAGATION AND EXECUTION WAKEUP MATRIX CIRCUIT IN A PROCESSOR Dec 23, 2020 Pending
Array ( [id] => 17507410 [patent_doc_number] => 20220100513 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-31 [patent_title] => APPARATUSES, METHODS, AND SYSTEMS FOR INSTRUCTIONS FOR LOADING DATA AND PADDING INTO A TILE OF A MATRIX OPERATIONS ACCELERATOR [patent_app_type] => utility [patent_app_number] => 17/134085 [patent_app_country] => US [patent_app_date] => 2020-12-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 29995 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17134085 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/134085
APPARATUSES, METHODS, AND SYSTEMS FOR INSTRUCTIONS FOR LOADING DATA AND PADDING INTO A TILE OF A MATRIX OPERATIONS ACCELERATOR Dec 23, 2020 Abandoned
Array ( [id] => 17690369 [patent_doc_number] => 20220197662 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-23 [patent_title] => Accessing A Branch Target Buffer Based On Branch Instruction Information [patent_app_type] => utility [patent_app_number] => 17/130028 [patent_app_country] => US [patent_app_date] => 2020-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11718 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17130028 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/130028
Accessing A Branch Target Buffer Based On Branch Instruction Information Dec 21, 2020 Abandoned
Array ( [id] => 19626088 [patent_doc_number] => 12164921 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-12-10 [patent_title] => Comparing hash values computed at function entry and exit for increased security [patent_app_type] => utility [patent_app_number] => 17/123711 [patent_app_country] => US [patent_app_date] => 2020-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 10127 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 302 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17123711 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/123711
Comparing hash values computed at function entry and exit for increased security Dec 15, 2020 Issued
Array ( [id] => 16918631 [patent_doc_number] => 20210191723 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-24 [patent_title] => CHIP INCLUDING PROCESSOR AND EXCEPTION HANDLING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/123723 [patent_app_country] => US [patent_app_date] => 2020-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6065 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17123723 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/123723
CHIP INCLUDING PROCESSOR AND EXCEPTION HANDLING METHOD THEREOF Dec 15, 2020 Abandoned
Array ( [id] => 16887451 [patent_doc_number] => 20210173648 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-10 [patent_title] => PROCESSOR FOR NEURAL NETWORK OPERATION [patent_app_type] => utility [patent_app_number] => 17/108470 [patent_app_country] => US [patent_app_date] => 2020-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6393 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17108470 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/108470
PROCESSOR FOR NEURAL NETWORK OPERATION Nov 30, 2020 Abandoned
Array ( [id] => 17581114 [patent_doc_number] => 20220137969 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-05 [patent_title] => MULTI-VENDOR ACCELERATOR MANAGEMENT PROTOCOL INTEROPERABILITY [patent_app_type] => utility [patent_app_number] => 17/084404 [patent_app_country] => US [patent_app_date] => 2020-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4070 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17084404 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/084404
MULTI-VENDOR ACCELERATOR MANAGEMENT PROTOCOL INTEROPERABILITY Oct 28, 2020 Abandoned
Array ( [id] => 19725783 [patent_doc_number] => 20250028534 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-23 [patent_title] => MECHANISM FOR EFFICIENT MASSIVELY-CONCURRENT CONDITIONAL COMPUTATION [patent_app_type] => utility [patent_app_number] => 17/076280 [patent_app_country] => US [patent_app_date] => 2020-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8398 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17076280 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/076280
MECHANISM FOR EFFICIENT MASSIVELY-CONCURRENT CONDITIONAL COMPUTATION Oct 20, 2020 Pending
Array ( [id] => 19198208 [patent_doc_number] => 11995447 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-05-28 [patent_title] => Quick predictor override and update by a BTAC [patent_app_type] => utility [patent_app_number] => 17/071560 [patent_app_country] => US [patent_app_date] => 2020-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6019 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 245 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17071560 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/071560
Quick predictor override and update by a BTAC Oct 14, 2020 Issued
Array ( [id] => 18493373 [patent_doc_number] => 11698789 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-07-11 [patent_title] => Restoring speculative history used for making speculative predictions for instructions processed in a processor employing control independence techniques [patent_app_type] => utility [patent_app_number] => 17/068253 [patent_app_country] => US [patent_app_date] => 2020-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 17 [patent_no_of_words] => 14465 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 280 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17068253 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/068253
Restoring speculative history used for making speculative predictions for instructions processed in a processor employing control independence techniques Oct 11, 2020 Issued
Array ( [id] => 16600103 [patent_doc_number] => 20210026634 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-01-28 [patent_title] => APPARATUS WITH REDUCED HARDWARE REGISTER SET USING REGISTER-EMULATING MEMORY LOCATION TO EMULATE ARCHITECTURAL REGISTER [patent_app_type] => utility [patent_app_number] => 17/067852 [patent_app_country] => US [patent_app_date] => 2020-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12751 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17067852 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/067852
APPARATUS WITH REDUCED HARDWARE REGISTER SET USING REGISTER-EMULATING MEMORY LOCATION TO EMULATE ARCHITECTURAL REGISTER Oct 11, 2020 Pending
Array ( [id] => 16887456 [patent_doc_number] => 20210173653 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-10 [patent_title] => INSTRUCTION PREFETCHING METHOD, DEVICE AND MEDIUM [patent_app_type] => utility [patent_app_number] => 17/036596 [patent_app_country] => US [patent_app_date] => 2020-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7051 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17036596 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/036596
Method and apparatus for instruction prefetching with alternating buffers and sequential instruction address matching Sep 28, 2020 Issued
Array ( [id] => 19917820 [patent_doc_number] => 12293190 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-05-06 [patent_title] => Managing commit order for an external instruction relative to queued instructions [patent_app_type] => utility [patent_app_number] => 17/036028 [patent_app_country] => US [patent_app_date] => 2020-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 0 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 221 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17036028 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/036028
Managing commit order for an external instruction relative to queued instructions Sep 28, 2020 Issued
Array ( [id] => 16722159 [patent_doc_number] => 20210089306 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-25 [patent_title] => INSTRUCTION PROCESSING METHOD AND APPARATUS [patent_app_type] => utility [patent_app_number] => 17/029595 [patent_app_country] => US [patent_app_date] => 2020-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13982 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -25 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17029595 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/029595
INSTRUCTION PROCESSING METHOD AND APPARATUS Sep 22, 2020 Abandoned
Array ( [id] => 17446273 [patent_doc_number] => 20220066778 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-03 [patent_title] => ELECTRONIC APPARATUS AND METHOD FOR REDUCING NUMBER OF COMMANDS [patent_app_type] => utility [patent_app_number] => 17/028966 [patent_app_country] => US [patent_app_date] => 2020-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6443 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17028966 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/028966
Reducing a number of commands transmitted to a co-processor by merging register-setting commands having address continuity Sep 21, 2020 Issued
Array ( [id] => 16714059 [patent_doc_number] => 20210081206 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-18 [patent_title] => PROGRAMMABLE ELECTRONIC DEVICES AND METHODS OF OPERATING THEREOF [patent_app_type] => utility [patent_app_number] => 17/021819 [patent_app_country] => US [patent_app_date] => 2020-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6266 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 38 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17021819 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/021819
PROGRAMMABLE ELECTRONIC DEVICES AND METHODS OF OPERATING THEREOF Sep 14, 2020 Pending
Array ( [id] => 17446325 [patent_doc_number] => 20220066830 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-03 [patent_title] => COMPACTION OF ARCHITECTED REGISTERS IN A SIMULTANEOUS MULTITHREADING PROCESSOR [patent_app_type] => utility [patent_app_number] => 17/004573 [patent_app_country] => US [patent_app_date] => 2020-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8325 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17004573 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/004573
Compaction of architected registers in a simultaneous multithreading processor Aug 26, 2020 Issued
Array ( [id] => 17810423 [patent_doc_number] => 20220262258 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-08-18 [patent_title] => AN AVIONIC COMPUTER ARCHITECTURE [patent_app_type] => utility [patent_app_number] => 17/625051 [patent_app_country] => US [patent_app_date] => 2020-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3482 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 248 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17625051 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/625051
AN AVIONIC COMPUTER ARCHITECTURE Aug 23, 2020 Abandoned
Array ( [id] => 17430315 [patent_doc_number] => 20220058024 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-02-24 [patent_title] => USING TAGGED INSTRUCTION EXTENSION TO EXPRESS DEPENDENCY FOR MEMORY-BASED ACCELERATOR INSTRUCTIONS [patent_app_type] => utility [patent_app_number] => 16/996710 [patent_app_country] => US [patent_app_date] => 2020-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4411 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16996710 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/996710
USING TAGGED INSTRUCTION EXTENSION TO EXPRESS DEPENDENCY FOR MEMORY-BASED ACCELERATOR INSTRUCTIONS Aug 17, 2020 Abandoned
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