Search

David J. Huisman

Examiner (ID: 4847, Phone: (571)272-4168 , Office: P/2183 )

Most Active Art Unit
2183
Art Unit(s)
2183
Total Applications
930
Issued Applications
493
Pending Applications
141
Abandoned Applications
335

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16470342 [patent_doc_number] => 20200371879 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-11-26 [patent_title] => DATA STORAGE RESOURCE ALLOCATION BY PERFORMING ABBREVIATED RESOURCE CHECKS OF CERTAIN DATA STORAGE RESOURCES TO DETRMINE WHETHER DATA STORAGE REQUESTS WOULD FAIL [patent_app_type] => utility [patent_app_number] => 16/991899 [patent_app_country] => US [patent_app_date] => 2020-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8787 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 227 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16991899 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/991899
DATA STORAGE RESOURCE ALLOCATION BY PERFORMING ABBREVIATED RESOURCE CHECKS OF CERTAIN DATA STORAGE RESOURCES TO DETRMINE WHETHER DATA STORAGE REQUESTS WOULD FAIL Aug 11, 2020 Pending
Array ( [id] => 17358640 [patent_doc_number] => 20220019436 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-01-20 [patent_title] => FUSION OF MICROPROCESSOR STORE INSTRUCTIONS [patent_app_type] => utility [patent_app_number] => 16/933241 [patent_app_country] => US [patent_app_date] => 2020-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8429 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16933241 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/933241
FUSION OF MICROPROCESSOR STORE INSTRUCTIONS Jul 19, 2020 Pending
Array ( [id] => 18052968 [patent_doc_number] => 11526352 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-12-13 [patent_title] => Hardware processor and method for loading a microcode patch from cache into patch memory and reloading an overwritten micro-operation [patent_app_type] => utility [patent_app_number] => 16/932682 [patent_app_country] => US [patent_app_date] => 2020-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 31 [patent_no_of_words] => 29356 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16932682 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/932682
Hardware processor and method for loading a microcode patch from cache into patch memory and reloading an overwritten micro-operation Jul 16, 2020 Issued
Array ( [id] => 19398850 [patent_doc_number] => 12073221 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-08-27 [patent_title] => Context switching method and system for swapping contexts between register sets based on thread halt [patent_app_type] => utility [patent_app_number] => 16/929079 [patent_app_country] => US [patent_app_date] => 2020-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 9298 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 393 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16929079 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/929079
Context switching method and system for swapping contexts between register sets based on thread halt Jul 13, 2020 Issued
Array ( [id] => 19122747 [patent_doc_number] => 11966736 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-04-23 [patent_title] => Interconnect device for selectively accumulating read data and aggregating processing results transferred between a processor core and memory [patent_app_type] => utility [patent_app_number] => 16/922257 [patent_app_country] => US [patent_app_date] => 2020-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 10893 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 241 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16922257 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/922257
Interconnect device for selectively accumulating read data and aggregating processing results transferred between a processor core and memory Jul 6, 2020 Issued
Array ( [id] => 17216379 [patent_doc_number] => 20210349717 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-11-11 [patent_title] => COMPACTION OF DIVERGED LANES FOR EFFICIENT USE OF ALUS [patent_app_type] => utility [patent_app_number] => 16/914030 [patent_app_country] => US [patent_app_date] => 2020-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 26386 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16914030 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/914030
COMPACTION OF DIVERGED LANES FOR EFFICIENT USE OF ALUS Jun 25, 2020 Abandoned
Array ( [id] => 18532025 [patent_doc_number] => 20230237097 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-07-27 [patent_title] => INFORMATION PROCESSING DEVICE, INFORMATION PROCESSING METHOD, AND RECORDING MEDIUM [patent_app_type] => utility [patent_app_number] => 18/010948 [patent_app_country] => US [patent_app_date] => 2020-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5392 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18010948 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/010948
Decision tree node instruction unification for parallel processing Jun 24, 2020 Issued
Array ( [id] => 16623472 [patent_doc_number] => 20210042125 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-02-11 [patent_title] => ELECTRONIC DEVICE FOR EXECUTING INSTRUCTIONS USING PROCESSOR CORES AND VARIOUS VERSIONS OF INSTRUCTION SET ARCHITECTURES [patent_app_type] => utility [patent_app_number] => 16/911907 [patent_app_country] => US [patent_app_date] => 2020-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9440 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16911907 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/911907
ELECTRONIC DEVICE FOR EXECUTING INSTRUCTIONS USING PROCESSOR CORES AND VARIOUS VERSIONS OF INSTRUCTION SET ARCHITECTURES Jun 24, 2020 Abandoned
Array ( [id] => 19062167 [patent_doc_number] => 11941403 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-03-26 [patent_title] => Selective prediction based on correlation between a given instruction and a subset of a set of monitored instructions ordinarily used to generate predictions for that given instruction [patent_app_type] => utility [patent_app_number] => 16/906259 [patent_app_country] => US [patent_app_date] => 2020-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 9436 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 258 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16906259 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/906259
Selective prediction based on correlation between a given instruction and a subset of a set of monitored instructions ordinarily used to generate predictions for that given instruction Jun 18, 2020 Issued
Array ( [id] => 17301615 [patent_doc_number] => 20210397454 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-23 [patent_title] => INSTRUCTION TO VECTORIZE LOOPS WITH BACKWARD CROSS-ITERATION DEPENDENCIES [patent_app_type] => utility [patent_app_number] => 16/905914 [patent_app_country] => US [patent_app_date] => 2020-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11833 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16905914 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/905914
INSTRUCTION TO VECTORIZE LOOPS WITH BACKWARD CROSS-ITERATION DEPENDENCIES Jun 17, 2020 Abandoned
Array ( [id] => 17276519 [patent_doc_number] => 20210382717 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-09 [patent_title] => HIERARCHICAL THREAD SCHEDULING [patent_app_type] => utility [patent_app_number] => 16/892202 [patent_app_country] => US [patent_app_date] => 2020-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 25878 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16892202 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/892202
HIERARCHICAL THREAD SCHEDULING Jun 2, 2020 Pending
Array ( [id] => 16423908 [patent_doc_number] => 20200349106 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-11-05 [patent_title] => MIXED-PRECISION NEURAL-PROCESSING UNIT TILE [patent_app_type] => utility [patent_app_number] => 16/847504 [patent_app_country] => US [patent_app_date] => 2020-04-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7206 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 328 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16847504 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/847504
Neural-processing unit tile for shuffling queued nibbles for multiplication with non-zero weight nibbles Apr 12, 2020 Issued
Array ( [id] => 16208886 [patent_doc_number] => 20200241876 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-30 [patent_title] => Range Mapping of Input Operands for Transcendental Functions [patent_app_type] => utility [patent_app_number] => 16/847068 [patent_app_country] => US [patent_app_date] => 2020-04-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7437 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16847068 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/847068
Range Mapping of Input Operands for Transcendental Functions Apr 12, 2020 Abandoned
Array ( [id] => 17128534 [patent_doc_number] => 20210303303 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-30 [patent_title] => SPECULATIVE EXECUTION FOLLOWING A STATE TRANSITION INSTRUCTION [patent_app_type] => utility [patent_app_number] => 16/827852 [patent_app_country] => US [patent_app_date] => 2020-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11792 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16827852 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/827852
Speculative execution following a state transition instruction Mar 23, 2020 Issued
Array ( [id] => 18291299 [patent_doc_number] => 11620169 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-04-04 [patent_title] => Barrierless and fenceless shared memory synchronization with write flag toggling [patent_app_type] => utility [patent_app_number] => 16/818845 [patent_app_country] => US [patent_app_date] => 2020-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 13488 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16818845 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/818845
Barrierless and fenceless shared memory synchronization with write flag toggling Mar 12, 2020 Issued
Array ( [id] => 16314714 [patent_doc_number] => 20200293452 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-09-17 [patent_title] => MEMORY DEVICE AND METHOD INCLUDING CIRCULAR INSTRUCTION MEMORY QUEUE [patent_app_type] => utility [patent_app_number] => 16/814236 [patent_app_country] => US [patent_app_date] => 2020-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10745 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16814236 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/814236
Memory device and method including processor-in-memory with circular instruction memory queue Mar 9, 2020 Issued
Array ( [id] => 16095383 [patent_doc_number] => 20200201678 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-06-25 [patent_title] => Multi-Phased and Multi-Threaded Program Execution Based on SIMD Ratio [patent_app_type] => utility [patent_app_number] => 16/805727 [patent_app_country] => US [patent_app_date] => 2020-02-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3089 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16805727 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/805727
Multi-phased and multi-threaded program execution based on SIMD ratio Feb 28, 2020 Issued
Array ( [id] => 19925169 [patent_doc_number] => 12299455 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2025-05-13 [patent_title] => Reconfigurable interconnect with multiplexer for flexible processor partitioning in a server computer [patent_app_type] => utility [patent_app_number] => 16/795264 [patent_app_country] => US [patent_app_date] => 2020-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 15 [patent_no_of_words] => 7007 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 447 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16795264 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/795264
Reconfigurable interconnect with multiplexer for flexible processor partitioning in a server computer Feb 18, 2020 Issued
Array ( [id] => 18154795 [patent_doc_number] => 11567773 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-01-31 [patent_title] => Memory controller and memory system for generating instruction set based on non-interleaving block group information [patent_app_type] => utility [patent_app_number] => 16/745810 [patent_app_country] => US [patent_app_date] => 2020-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 8358 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 300 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16745810 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/745810
Memory controller and memory system for generating instruction set based on non-interleaving block group information Jan 16, 2020 Issued
Array ( [id] => 16964828 [patent_doc_number] => 20210216327 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-15 [patent_title] => REACH MATRIX SCHEDULER CIRCUIT FOR SCHEDULING OF INSTRUCTIONS TO BE EXECUTED IN A PROCESSOR [patent_app_type] => utility [patent_app_number] => 16/738362 [patent_app_country] => US [patent_app_date] => 2020-01-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15115 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16738362 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/738362
Reach matrix scheduler circuit for scheduling instructions to be executed in a processor Jan 8, 2020 Issued
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