David J. Lee

Array ( [id] => 5956737 [patent_doc_number] => 20110035555 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-02-10 [patent_title] => 'METHOD AND APPARATUS FOR AFFINITY-GUIDED SPECULATIVE HELPER THREADS IN CHIP MULTIPROCESSORS' [patent_app_type] => utility [patent_app_number] => 12/909774 [patent_app_country] => US [patent_app_date] => 2010-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7797 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0035/20110035555.pdf [firstpage_image] =>[orig_patent_app_number] => 12909774 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6647792 [patent_doc_number] => 20100037037 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-02-11 [patent_title] => 'METHOD FOR INSTRUCTION PIPELINING ON IRREGULAR REGISTER FILES' [patent_app_type] => utility [patent_app_number] => 12/490932 [patent_app_country] => US [patent_app_date] => 2009-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2554 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0037/20100037037.pdf [firstpage_image] =>[orig_patent_app_number] => 12490932 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4447452 [patent_doc_number] => 07930524 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-04-19 [patent_title] => 'Method for executing a 32-bit flat address program during a system management mode interrupt' [patent_app_type] => utility [patent_app_number] => 12/247158 [patent_app_country] => US [patent_app_date] => 2008-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 1381 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/930/07930524.pdf [firstpage_image] =>[orig_patent_app_number] => 12247158 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6647426 [patent_doc_number] => 20100036987 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-02-11 [patent_title] => 'Apparatus and Methods for Speculative Interrupt Vector Prefetching' [patent_app_type] => utility [patent_app_number] => 12/188626 [patent_app_country] => US [patent_app_date] => 2008-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6982 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0036/20100036987.pdf [firstpage_image] =>[orig_patent_app_number] => 12188626 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8087523 [patent_doc_number] => 08151096 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-04-03 [patent_title] => 'Method to improve branch prediction latency' [patent_app_type] => utility [patent_app_number] => 12/187126 [patent_app_country] => US [patent_app_date] => 2008-08-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 4975 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/151/08151096.pdf [firstpage_image] =>[orig_patent_app_number] => 12187126 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7532568 [patent_doc_number] => 07844802 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-11-30 [patent_title] => 'Instructions for ordering execution in pipelined processes' [patent_app_type] => utility [patent_app_number] => 12/145204 [patent_app_country] => US [patent_app_date] => 2008-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 4174 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/844/07844802.pdf [firstpage_image] =>[orig_patent_app_number] => 12145204 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4730428 [patent_doc_number] => 20080209163 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-08-28 [patent_title] => 'DATA PROCESSING SYSTEM WITH BACKPLANE AND PROCESSOR BOOKS CONFIGURABLE TO SUPPPRT BOTH TECHNICAL AND COMMERCIAL WORKLOADS' [patent_app_type] => utility [patent_app_number] => 12/118199 [patent_app_country] => US [patent_app_date] => 2008-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6698 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0209/20080209163.pdf [firstpage_image] =>[orig_patent_app_number] => 12118199 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6029384 [patent_doc_number] => 20110054876 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-03-03 [patent_title] => 'PHYSICAL REALIZATIONS OF A UNIVERSAL ADIABATIC QUANTUM COMPUTER' [patent_app_type] => utility [patent_app_number] => 12/098348 [patent_app_country] => US [patent_app_date] => 2008-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 11100 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0054/20110054876.pdf [firstpage_image] =>[orig_patent_app_number] => 12098348 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4684009 [patent_doc_number] => 20080250235 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-09 [patent_title] => 'Microcomputer and method of setting operation of microcomputer' [patent_app_type] => utility [patent_app_number] => 12/078621 [patent_app_country] => US [patent_app_date] => 2008-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 5780 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0250/20080250235.pdf [firstpage_image] =>[orig_patent_app_number] => 12078621 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5405599 [patent_doc_number] => 20090240914 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-09-24 [patent_title] => 'RECYCLING LONG MULTI-OPERAND INSTRUCTIONS' [patent_app_type] => utility [patent_app_number] => 12/051215 [patent_app_country] => US [patent_app_date] => 2008-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4889 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0240/20090240914.pdf [firstpage_image] =>[orig_patent_app_number] => 12051215 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4606357 [patent_doc_number] => 07987343 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-07-26 [patent_title] => 'Processor and method for synchronous load multiple fetching sequence and pipeline stage result tracking to facilitate early address generation interlock bypass' [patent_app_type] => utility [patent_app_number] => 12/051527 [patent_app_country] => US [patent_app_date] => 2008-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 3770 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/987/07987343.pdf [firstpage_image] =>[orig_patent_app_number] => 12051527 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5405614 [patent_doc_number] => 20090240929 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-09-24 [patent_title] => 'METHOD, SYSTEM AND COMPUTER PROGRAM PRODUCT FOR REDUCED OVERHEAD ADDRESS MODE CHANGE MANAGEMENT IN A PIPELINED, RECYLING MICROPROCESSOR' [patent_app_type] => utility [patent_app_number] => 12/051415 [patent_app_country] => US [patent_app_date] => 2008-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2481 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0240/20090240929.pdf [firstpage_image] =>[orig_patent_app_number] => 12051415 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8378236 [patent_doc_number] => 08261047 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-09-04 [patent_title] => 'Qualification of conditional debug instructions based on address' [patent_app_type] => utility [patent_app_number] => 12/049984 [patent_app_country] => US [patent_app_date] => 2008-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5889 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 46 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12049984 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5387447 [patent_doc_number] => 20090228692 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-09-10 [patent_title] => 'Load Register Instruction Short Circuiting Method' [patent_app_type] => utility [patent_app_number] => 12/044013 [patent_app_country] => US [patent_app_date] => 2008-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 1670 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0228/20090228692.pdf [firstpage_image] =>[orig_patent_app_number] => 12044013 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5418105 [patent_doc_number] => 20090043992 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-02-12 [patent_title] => 'Method And System For Data Speculation On Multicore Systems' [patent_app_type] => utility [patent_app_number] => 12/034741 [patent_app_country] => US [patent_app_date] => 2008-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8002 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0043/20090043992.pdf [firstpage_image] =>[orig_patent_app_number] => 12034741 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4683990 [patent_doc_number] => 20080250216 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-09 [patent_title] => 'Protected function calling' [patent_app_type] => utility [patent_app_number] => 12/068448 [patent_app_country] => US [patent_app_date] => 2008-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6880 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0250/20080250216.pdf [firstpage_image] =>[orig_patent_app_number] => 12068448 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5528886 [patent_doc_number] => 20090198963 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-08-06 [patent_title] => 'COMPLETION OF ASYNCHRONOUS MEMORY MOVE IN THE PRESENCE OF A BARRIER OPERATION' [patent_app_type] => utility [patent_app_number] => 12/024513 [patent_app_country] => US [patent_app_date] => 2008-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 14131 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0198/20090198963.pdf [firstpage_image] =>[orig_patent_app_number] => 12024513 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4895270 [patent_doc_number] => 20080104370 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-05-01 [patent_title] => 'RISC type of CPU and compiler to produce object program executed by the same' [patent_app_type] => utility [patent_app_number] => 11/998966 [patent_app_country] => US [patent_app_date] => 2007-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 9184 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0104/20080104370.pdf [firstpage_image] =>[orig_patent_app_number] => 11998966 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 200859 [patent_doc_number] => 07640417 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-12-29 [patent_title] => 'Instruction length decoder' [patent_app_type] => utility [patent_app_number] => 11/865071 [patent_app_country] => US [patent_app_date] => 2007-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2420 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/640/07640417.pdf [firstpage_image] =>[orig_patent_app_number] => 11865071 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 106850 [patent_doc_number] => 07730289 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-06-01 [patent_title] => 'Method for preloading data in a CPU pipeline' [patent_app_type] => utility [patent_app_number] => 11/862816 [patent_app_country] => US [patent_app_date] => 2007-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3059 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/730/07730289.pdf [firstpage_image] =>[orig_patent_app_number] => 11862816 [rel_patent_id] =>[rel_patent_doc_number] =>)