Search

David J. Lee

Examiner (ID: 8253, Phone: (571)270-7134 , Office: P/2693 )

Most Active Art Unit
2693
Art Unit(s)
2633, 2693, 2629, 2613, 2625, 2695
Total Applications
248
Issued Applications
126
Pending Applications
3
Abandoned Applications
120

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 7321214 [patent_doc_number] => 20040225847 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-11-11 [patent_title] => 'Systems and methods for scheduling memory requests utilizing multi-level arbitration' [patent_app_type] => new [patent_app_number] => 10/434044 [patent_app_country] => US [patent_app_date] => 2003-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2207 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0225/20040225847.pdf [firstpage_image] =>[orig_patent_app_number] => 10434044 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/434044
Systems and methods for scheduling memory requests utilizing multi-level arbitration May 7, 2003 Issued
Array ( [id] => 623288 [patent_doc_number] => 07143267 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-11-28 [patent_title] => 'Partitioning prefetch registers to prevent at least in part inconsistent prefetch information from being stored in a prefetch register of a multithreading processor' [patent_app_type] => utility [patent_app_number] => 10/425424 [patent_app_country] => US [patent_app_date] => 2003-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6569 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 314 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/143/07143267.pdf [firstpage_image] =>[orig_patent_app_number] => 10425424 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/425424
Partitioning prefetch registers to prevent at least in part inconsistent prefetch information from being stored in a prefetch register of a multithreading processor Apr 27, 2003 Issued
Array ( [id] => 7300377 [patent_doc_number] => 20040215926 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-10-28 [patent_title] => 'Data processing system having novel interconnect for supporting both technical and commercial workloads' [patent_app_type] => new [patent_app_number] => 10/425421 [patent_app_country] => US [patent_app_date] => 2003-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6719 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 217 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0215/20040215926.pdf [firstpage_image] =>[orig_patent_app_number] => 10425421 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/425421
Data processing system with backplane and processor books configurable to support both technical and commercial workloads Apr 27, 2003 Issued
Array ( [id] => 7300387 [patent_doc_number] => 20040215929 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-10-28 [patent_title] => 'Cross-chip communication mechanism in distributed node topology' [patent_app_type] => new [patent_app_number] => 10/425397 [patent_app_country] => US [patent_app_date] => 2003-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4665 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0215/20040215929.pdf [firstpage_image] =>[orig_patent_app_number] => 10425397 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/425397
Cross-chip communication mechanism in distributed node topology to access free-running scan registers in clock-controlled components Apr 27, 2003 Issued
Array ( [id] => 7300394 [patent_doc_number] => 20040215932 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-10-28 [patent_title] => 'Method and logical apparatus for managing thread execution in a simultaneous multi-threaded (SMT) processor' [patent_app_type] => new [patent_app_number] => 10/422648 [patent_app_country] => US [patent_app_date] => 2003-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3478 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0215/20040215932.pdf [firstpage_image] =>[orig_patent_app_number] => 10422648 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/422648
Method and logical apparatus for switching between single-threaded and multi-threaded execution states in a simultaneous multi-threaded (SMT) processor Apr 23, 2003 Issued
Array ( [id] => 7300404 [patent_doc_number] => 20040215941 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-10-28 [patent_title] => 'Method and system to handle register window fill and spill' [patent_app_type] => new [patent_app_number] => 10/422174 [patent_app_country] => US [patent_app_date] => 2003-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6088 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 13 [patent_words_short_claim] => 23 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0215/20040215941.pdf [firstpage_image] =>[orig_patent_app_number] => 10422174 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/422174
Method and system to handle register window fill and spill Apr 23, 2003 Abandoned
Array ( [id] => 581891 [patent_doc_number] => 07159097 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-01-02 [patent_title] => 'Apparatus and method for buffering instructions and late-generated related information using history of previous load/shifts' [patent_app_type] => utility [patent_app_number] => 10/422057 [patent_app_country] => US [patent_app_date] => 2003-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 8319 [patent_no_of_claims] => 41 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/159/07159097.pdf [firstpage_image] =>[orig_patent_app_number] => 10422057 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/422057
Apparatus and method for buffering instructions and late-generated related information using history of previous load/shifts Apr 22, 2003 Issued
Array ( [id] => 7076728 [patent_doc_number] => 20050149556 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-07-07 [patent_title] => 'Operation processor, building method, operation processing system, and operation processing method' [patent_app_type] => utility [patent_app_number] => 10/508802 [patent_app_country] => US [patent_app_date] => 2003-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 26704 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0149/20050149556.pdf [firstpage_image] =>[orig_patent_app_number] => 10508802 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/508802
Operation processing device, system and method having register-to-register addressing Mar 25, 2003 Issued
Array ( [id] => 7672276 [patent_doc_number] => 20040181503 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-09-16 [patent_title] => 'Information storage and retrieval method and apparatus' [patent_app_type] => new [patent_app_number] => 10/387687 [patent_app_country] => US [patent_app_date] => 2003-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3136 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0181/20040181503.pdf [firstpage_image] =>[orig_patent_app_number] => 10387687 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/387687
Information storage and retrieval method and apparatus Mar 12, 2003 Abandoned
Array ( [id] => 536374 [patent_doc_number] => 07191316 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-03-13 [patent_title] => 'Method and a system for using same set of registers to handle both single and double precision floating point instructions in an instruction stream' [patent_app_type] => utility [patent_app_number] => 10/353662 [patent_app_country] => US [patent_app_date] => 2003-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 5114 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 304 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/191/07191316.pdf [firstpage_image] =>[orig_patent_app_number] => 10353662 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/353662
Method and a system for using same set of registers to handle both single and double precision floating point instructions in an instruction stream Jan 28, 2003 Issued
Array ( [id] => 7291021 [patent_doc_number] => 20040148489 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-07-29 [patent_title] => 'Sideband VLIW processor' [patent_app_type] => new [patent_app_number] => 10/352588 [patent_app_country] => US [patent_app_date] => 2003-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5522 [patent_no_of_claims] => 49 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 29 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0148/20040148489.pdf [firstpage_image] =>[orig_patent_app_number] => 10352588 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/352588
Sideband VLIW processor Jan 27, 2003 Abandoned
Array ( [id] => 343149 [patent_doc_number] => 07502910 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-03-10 [patent_title] => 'Sideband scout thread processor for reducing latency associated with a main processor' [patent_app_type] => utility [patent_app_number] => 10/352495 [patent_app_country] => US [patent_app_date] => 2003-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 6332 [patent_no_of_claims] => 56 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/502/07502910.pdf [firstpage_image] =>[orig_patent_app_number] => 10352495 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/352495
Sideband scout thread processor for reducing latency associated with a main processor Jan 27, 2003 Issued
Array ( [id] => 7291038 [patent_doc_number] => 20040148496 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-07-29 [patent_title] => 'Method for handling a conditional move instruction in an out of order multi-issue processor' [patent_app_type] => new [patent_app_number] => 10/351902 [patent_app_country] => US [patent_app_date] => 2003-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5103 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0148/20040148496.pdf [firstpage_image] =>[orig_patent_app_number] => 10351902 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/351902
Method for handling a conditional move instruction in an out of order multi-issue processor Jan 26, 2003 Abandoned
Array ( [id] => 163310 [patent_doc_number] => 07676650 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-03-09 [patent_title] => 'Apparatus for controlling instruction fetch reusing fetched instruction' [patent_app_type] => utility [patent_app_number] => 10/347193 [patent_app_country] => US [patent_app_date] => 2003-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 17 [patent_no_of_words] => 6429 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/676/07676650.pdf [firstpage_image] =>[orig_patent_app_number] => 10347193 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/347193
Apparatus for controlling instruction fetch reusing fetched instruction Jan 20, 2003 Issued
Array ( [id] => 231463 [patent_doc_number] => 07603545 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-10-13 [patent_title] => 'Instruction control method and processor to process instructions by out-of-order processing using delay instructions for branching' [patent_app_type] => utility [patent_app_number] => 10/345296 [patent_app_country] => US [patent_app_date] => 2003-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 8503 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/603/07603545.pdf [firstpage_image] =>[orig_patent_app_number] => 10345296 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/345296
Instruction control method and processor to process instructions by out-of-order processing using delay instructions for branching Jan 15, 2003 Issued
Array ( [id] => 7328718 [patent_doc_number] => 20040139300 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-07-15 [patent_title] => 'Result forwarding in a superscalar processor' [patent_app_type] => new [patent_app_number] => 10/341995 [patent_app_country] => US [patent_app_date] => 2003-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2192 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0139/20040139300.pdf [firstpage_image] =>[orig_patent_app_number] => 10341995 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/341995
Result forwarding in a superscalar processor Jan 13, 2003 Abandoned
Array ( [id] => 7372598 [patent_doc_number] => 20040006684 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-01-08 [patent_title] => 'Instruction execution apparatus' [patent_app_type] => new [patent_app_number] => 10/331917 [patent_app_country] => US [patent_app_date] => 2002-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 6917 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 198 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0006/20040006684.pdf [firstpage_image] =>[orig_patent_app_number] => 10331917 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/331917
Instruction execution apparatus comprising a commit stack entry unit Dec 30, 2002 Issued
Array ( [id] => 166636 [patent_doc_number] => 07673121 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-03-02 [patent_title] => 'Circuit for monitoring a microprocessor and analysis tool and inputs/outputs thereof' [patent_app_type] => utility [patent_app_number] => 10/535063 [patent_app_country] => US [patent_app_date] => 2002-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 5 [patent_no_of_words] => 2796 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 249 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/673/07673121.pdf [firstpage_image] =>[orig_patent_app_number] => 10535063 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/535063
Circuit for monitoring a microprocessor and analysis tool and inputs/outputs thereof Nov 13, 2002 Issued
Array ( [id] => 6826344 [patent_doc_number] => 20030236966 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-12-25 [patent_title] => 'Fusing load and alu operations' [patent_app_type] => new [patent_app_number] => 10/180391 [patent_app_country] => US [patent_app_date] => 2002-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2560 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0236/20030236966.pdf [firstpage_image] =>[orig_patent_app_number] => 10180391 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/180391
Fusing load and alu operations Jun 24, 2002 Issued
Array ( [id] => 6826342 [patent_doc_number] => 20030236964 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-12-25 [patent_title] => 'Instruction length decoder' [patent_app_type] => new [patent_app_number] => 10/180389 [patent_app_country] => US [patent_app_date] => 2002-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2418 [patent_no_of_claims] => 49 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 22 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0236/20030236964.pdf [firstpage_image] =>[orig_patent_app_number] => 10180389 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/180389
Instruction length decoder Jun 24, 2002 Issued
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