David J. Pearson

Array ( [id] => 9668140 [patent_doc_number] => 20140232003 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-08-21 [patent_title] => 'Semiconductor Constructions, Semiconductor Processing Methods, Methods of Forming Contact Pads, and Methods of Forming Electrical Connections Between Metal-Containing Layers' [patent_app_type] => utility [patent_app_number] => 14/265609 [patent_app_country] => US [patent_app_date] => 2014-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 5841 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14265609 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9783183 [patent_doc_number] => 20140300003 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-10-09 [patent_title] => 'SEMICONDUCTOR DEVICE AND INTERCONNECT SUBSTRATE' [patent_app_type] => utility [patent_app_number] => 14/242462 [patent_app_country] => US [patent_app_date] => 2014-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 27 [patent_no_of_words] => 17012 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14242462 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9768171 [patent_doc_number] => 20140291833 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-10-02 [patent_title] => 'SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 14/225519 [patent_app_country] => US [patent_app_date] => 2014-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2936 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14225519 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9729242 [patent_doc_number] => 20140264949 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-09-18 [patent_title] => 'GOLD DIE BOND SHEET PREFORM' [patent_app_type] => utility [patent_app_number] => 14/205403 [patent_app_country] => US [patent_app_date] => 2014-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2663 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14205403 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9832427 [patent_doc_number] => 08941247 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2015-01-27 [patent_title] => 'Stacked die package for MEMS resonator system' [patent_app_type] => utility [patent_app_number] => 14/191978 [patent_app_country] => US [patent_app_date] => 2014-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5929 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14191978 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9648466 [patent_doc_number] => 08802475 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-08-12 [patent_title] => 'Method of fabricating a 3D integrated electronic device structure including increased thermal dissipation capabilities' [patent_app_type] => utility [patent_app_number] => 14/186362 [patent_app_country] => US [patent_app_date] => 2014-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 5875 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14186362 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9682721 [patent_doc_number] => 20140239484 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-08-28 [patent_title] => 'METHOD FOR FORMING SINTERED SILVER COATING FILM, BAKING APPARATUS, AND SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 14/184640 [patent_app_country] => US [patent_app_date] => 2014-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 9225 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14184640 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9608090 [patent_doc_number] => 08785255 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-07-22 [patent_title] => 'Substrate for mounting semiconductor, semiconductor device and method for manufacturing semiconductor device' [patent_app_type] => utility [patent_app_number] => 14/178357 [patent_app_country] => US [patent_app_date] => 2014-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 3480 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 208 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14178357 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9654271 [patent_doc_number] => 20140225276 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-08-14 [patent_title] => 'CHIP PACKAGE' [patent_app_type] => utility [patent_app_number] => 14/171734 [patent_app_country] => US [patent_app_date] => 2014-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3106 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14171734 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9508730 [patent_doc_number] => 20140145220 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-05-29 [patent_title] => 'LIGHT EMITTING DEVICE' [patent_app_type] => utility [patent_app_number] => 14/168439 [patent_app_country] => US [patent_app_date] => 2014-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 21567 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14168439 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9608908 [patent_doc_number] => 08786078 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-07-22 [patent_title] => 'Vehicles, power electronics modules and cooling apparatuses with single-phase and two-phase surface enhancement features' [patent_app_type] => utility [patent_app_number] => 14/143377 [patent_app_country] => US [patent_app_date] => 2013-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 4531 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14143377 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9370428 [patent_doc_number] => 20140080301 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-03-20 [patent_title] => 'FABRICATING A SEMICONDUCTOR DIE HAVING COEFFICIENT OF THERMAL EXPANSION GRADED LAYER' [patent_app_type] => utility [patent_app_number] => 14/089958 [patent_app_country] => US [patent_app_date] => 2013-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3490 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14089958 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9363254 [patent_doc_number] => 20140073127 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-03-13 [patent_title] => 'SEMICONDUCTOR DEVICE AND INFORMATION PROCESSING SYSTEM INCLUDING THE SAME' [patent_app_type] => utility [patent_app_number] => 14/082138 [patent_app_country] => US [patent_app_date] => 2013-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 12462 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14082138 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9597290 [patent_doc_number] => 20140193970 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-07-10 [patent_title] => 'ISOLATED WIRE STRUCTURES WITH REDUCED STRESS, METHODS OF MANUFACTURING AND DESIGN STRUCTURES' [patent_app_type] => utility [patent_app_number] => 14/076707 [patent_app_country] => US [patent_app_date] => 2013-11-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4281 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14076707 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9338987 [patent_doc_number] => 20140065769 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-03-06 [patent_title] => 'CHIP PACKAGE AND FABRICATION METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 14/074519 [patent_app_country] => US [patent_app_date] => 2013-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 3732 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14074519 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9330650 [patent_doc_number] => 20140057432 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-02-27 [patent_title] => 'SEMICONDUCTOR DEVICE INCLUDING COPPER WIRING AND VIA WIRING HAVING LENGTH LONGER THAN WIDTH THEREOF AND METHOD OF MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 14/067472 [patent_app_country] => US [patent_app_date] => 2013-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 3389 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14067472 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9306653 [patent_doc_number] => 20140045327 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-02-13 [patent_title] => 'Double Solid Metal Pad with Reduced Area' [patent_app_type] => utility [patent_app_number] => 14/058862 [patent_app_country] => US [patent_app_date] => 2013-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3482 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14058862 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9303957 [patent_doc_number] => 20140042631 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-02-13 [patent_title] => 'SEMICONDUCTOR COMPONENT COMPRISING COPPER METALLIZATIONS' [patent_app_type] => utility [patent_app_number] => 14/054749 [patent_app_country] => US [patent_app_date] => 2013-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 7718 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14054749 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9427523 [patent_doc_number] => 08703598 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-04-22 [patent_title] => 'Manufacturing method of lead frame substrate' [patent_app_type] => utility [patent_app_number] => 14/038114 [patent_app_country] => US [patent_app_date] => 2013-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 12 [patent_no_of_words] => 4540 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14038114 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9220365 [patent_doc_number] => 20140015140 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-01-16 [patent_title] => 'POWER MODULE SUBSTRATE, POWER MODULE, AND METHOD FOR MANUFACTURING POWER MODULE SUBSTRATE' [patent_app_type] => utility [patent_app_number] => 14/027601 [patent_app_country] => US [patent_app_date] => 2013-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 34 [patent_figures_cnt] => 34 [patent_no_of_words] => 25275 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14027601 [rel_patent_id] =>[rel_patent_doc_number] =>)