David L. Talbott

Array ( [id] => 2753745 [patent_doc_number] => 05021685 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-06-04 [patent_title] => 'Input buffer circuit having a resistor for reducing through-current and a capacitor for preventing delay' [patent_app_type] => 1 [patent_app_number] => 7/508460 [patent_app_country] => US [patent_app_date] => 1990-04-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 14 [patent_no_of_words] => 3824 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/021/05021685.pdf [firstpage_image] =>[orig_patent_app_number] => 508460 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2712000 [patent_doc_number] => 05055712 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-10-08 [patent_title] => 'Register file with programmable control, decode and/or data manipulation' [patent_app_type] => 1 [patent_app_number] => 7/504967 [patent_app_country] => US [patent_app_date] => 1990-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 17 [patent_no_of_words] => 4863 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 216 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/055/05055712.pdf [firstpage_image] =>[orig_patent_app_number] => 504967 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2712051 [patent_doc_number] => 05055715 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-10-08 [patent_title] => 'Semiconductor integrated circuit provided with monitor-elements for checking affection of process deviation on other elements' [patent_app_type] => 1 [patent_app_number] => 7/503642 [patent_app_country] => US [patent_app_date] => 1990-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 1656 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/055/05055715.pdf [firstpage_image] =>[orig_patent_app_number] => 503642 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2748096 [patent_doc_number] => 05023488 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-06-11 [patent_title] => 'Drivers and receivers for interfacing VLSI CMOS circuits to transmission lines' [patent_app_type] => 1 [patent_app_number] => 7/502372 [patent_app_country] => US [patent_app_date] => 1990-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 4038 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/023/05023488.pdf [firstpage_image] =>[orig_patent_app_number] => 502372 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2760149 [patent_doc_number] => 05043606 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-08-27 [patent_title] => 'Apparatus and method for programmably controlling the polarity of an I/O signal of a magnetic disk drive' [patent_app_type] => 1 [patent_app_number] => 7/502568 [patent_app_country] => US [patent_app_date] => 1990-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 3 [patent_no_of_words] => 2294 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/043/05043606.pdf [firstpage_image] =>[orig_patent_app_number] => 502568 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2674580 [patent_doc_number] => 05034635 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-07-23 [patent_title] => 'Positive to negative voltage translator circuit and method of operation' [patent_app_type] => 1 [patent_app_number] => 7/502477 [patent_app_country] => US [patent_app_date] => 1990-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 4576 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/034/05034635.pdf [firstpage_image] =>[orig_patent_app_number] => 502477 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2752803 [patent_doc_number] => 05038053 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-08-06 [patent_title] => 'Temperature-compensated integrated circuit for uniform current generation' [patent_app_type] => 1 [patent_app_number] => 7/497996 [patent_app_country] => US [patent_app_date] => 1990-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 1430 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/038/05038053.pdf [firstpage_image] =>[orig_patent_app_number] => 497996 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2771131 [patent_doc_number] => 05036216 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-07-30 [patent_title] => 'Video dot clock generator' [patent_app_type] => 1 [patent_app_number] => 7/490784 [patent_app_country] => US [patent_app_date] => 1990-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6053 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/036/05036216.pdf [firstpage_image] =>[orig_patent_app_number] => 490784 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2771284 [patent_doc_number] => 05036224 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-07-30 [patent_title] => 'Single ended MOS to ECL output buffer' [patent_app_type] => 1 [patent_app_number] => 7/487453 [patent_app_country] => US [patent_app_date] => 1990-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1915 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 372 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/036/05036224.pdf [firstpage_image] =>[orig_patent_app_number] => 487453 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2737700 [patent_doc_number] => 05051624 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-09-24 [patent_title] => 'High speed level converter to convert a TTL logic signal to a CMOS logic signal' [patent_app_type] => 1 [patent_app_number] => 7/484120 [patent_app_country] => US [patent_app_date] => 1990-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 2469 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/051/05051624.pdf [firstpage_image] =>[orig_patent_app_number] => 484120 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2749614 [patent_doc_number] => 05012133 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-04-30 [patent_title] => 'Circuit arrangement for processing sampled analog electrical signals' [patent_app_type] => 1 [patent_app_number] => 7/479502 [patent_app_country] => US [patent_app_date] => 1990-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 9675 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/012/05012133.pdf [firstpage_image] =>[orig_patent_app_number] => 479502 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2840545 [patent_doc_number] => 05120991 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-06-09 [patent_title] => 'Driver circuit for converting a CMOS level signal to a high-voltage level' [patent_app_type] => 1 [patent_app_number] => 7/457771 [patent_app_country] => US [patent_app_date] => 1990-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 4730 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 250 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/120/05120991.pdf [firstpage_image] =>[orig_patent_app_number] => 457771 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2728020 [patent_doc_number] => 05057702 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-10-15 [patent_title] => 'Duty radio control circuit apparatus' [patent_app_type] => 1 [patent_app_number] => 7/457875 [patent_app_country] => US [patent_app_date] => 1989-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 6695 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/057/05057702.pdf [firstpage_image] =>[orig_patent_app_number] => 457875 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2710693 [patent_doc_number] => 05001364 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-03-19 [patent_title] => 'Threshold crossing detector' [patent_app_type] => 1 [patent_app_number] => 7/448440 [patent_app_country] => US [patent_app_date] => 1989-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 6 [patent_no_of_words] => 2320 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/001/05001364.pdf [firstpage_image] =>[orig_patent_app_number] => 448440 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2753872 [patent_doc_number] => 05021692 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-06-04 [patent_title] => 'Integrator circuit' [patent_app_type] => 1 [patent_app_number] => 7/446518 [patent_app_country] => US [patent_app_date] => 1989-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 7285 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 225 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/021/05021692.pdf [firstpage_image] =>[orig_patent_app_number] => 446518 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2739700 [patent_doc_number] => 05077492 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-12-31 [patent_title] => 'BiCMOS circuitry having a combination CMOS gate and a bipolar transistor' [patent_app_type] => 1 [patent_app_number] => 7/440670 [patent_app_country] => US [patent_app_date] => 1989-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 25 [patent_no_of_words] => 6105 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/077/05077492.pdf [firstpage_image] =>[orig_patent_app_number] => 440670 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2747354 [patent_doc_number] => 05028822 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-07-02 [patent_title] => 'Circuit arrangement for processing analogue electrical signals' [patent_app_type] => 1 [patent_app_number] => 7/441140 [patent_app_country] => US [patent_app_date] => 1989-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 8869 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/028/05028822.pdf [firstpage_image] =>[orig_patent_app_number] => 441140 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2712019 [patent_doc_number] => 05055713 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-10-08 [patent_title] => 'Output circuit of semiconductor integrated circuit' [patent_app_type] => 1 [patent_app_number] => 7/438258 [patent_app_country] => US [patent_app_date] => 1989-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 10232 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/055/05055713.pdf [firstpage_image] =>[orig_patent_app_number] => 438258 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2699177 [patent_doc_number] => 04996452 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-02-26 [patent_title] => 'ECL/TTL tristate buffer' [patent_app_type] => 1 [patent_app_number] => 7/436846 [patent_app_country] => US [patent_app_date] => 1989-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2469 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/996/04996452.pdf [firstpage_image] =>[orig_patent_app_number] => 436846 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2686035 [patent_doc_number] => 05045729 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-09-03 [patent_title] => 'TTL/ECL translator circuit' [patent_app_type] => 1 [patent_app_number] => 7/436842 [patent_app_country] => US [patent_app_date] => 1989-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2022 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/045/05045729.pdf [firstpage_image] =>[orig_patent_app_number] => 436842 [rel_patent_id] =>[rel_patent_doc_number] =>)