David L. Talbott

Array ( [id] => 2852253 [patent_doc_number] => 05172400 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-12-15 [patent_title] => 'Frequency divider employing multiple stages of master/slave flip-flops' [patent_app_type] => 1 [patent_app_number] => 7/680240 [patent_app_country] => US [patent_app_date] => 1991-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 18 [patent_no_of_words] => 5345 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/172/05172400.pdf [firstpage_image] =>[orig_patent_app_number] => 680240 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2938509 [patent_doc_number] => 05187724 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-02-16 [patent_title] => 'Absolute position detecting device' [patent_app_type] => 1 [patent_app_number] => 7/679479 [patent_app_country] => US [patent_app_date] => 1991-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 4548 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/187/05187724.pdf [firstpage_image] =>[orig_patent_app_number] => 679479 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2841405 [patent_doc_number] => 05175753 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-12-29 [patent_title] => 'Counter cell including a latch circuit, control circuit and a pull-up circuit' [patent_app_type] => 1 [patent_app_number] => 7/678510 [patent_app_country] => US [patent_app_date] => 1991-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 4520 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 250 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/175/05175753.pdf [firstpage_image] =>[orig_patent_app_number] => 678510 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2865070 [patent_doc_number] => 05127036 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-06-30 [patent_title] => 'Fifty percent duty cycle divided-by-m counter' [patent_app_type] => 1 [patent_app_number] => 7/677913 [patent_app_country] => US [patent_app_date] => 1991-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 14 [patent_no_of_words] => 5765 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 208 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/127/05127036.pdf [firstpage_image] =>[orig_patent_app_number] => 677913 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2862856 [patent_doc_number] => 05134638 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-07-28 [patent_title] => 'Shift register connection between electrical circuits' [patent_app_type] => 1 [patent_app_number] => 7/678458 [patent_app_country] => US [patent_app_date] => 1991-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 2290 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/134/05134638.pdf [firstpage_image] =>[orig_patent_app_number] => 678458 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2990329 [patent_doc_number] => 05204884 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-04-20 [patent_title] => 'System for high-speed measurement and sorting of particles' [patent_app_type] => 1 [patent_app_number] => 7/671009 [patent_app_country] => US [patent_app_date] => 1991-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 4510 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/204/05204884.pdf [firstpage_image] =>[orig_patent_app_number] => 671009 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2904621 [patent_doc_number] => 05270979 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-12-14 [patent_title] => 'Method for optimum erasing of EEPROM' [patent_app_type] => 1 [patent_app_number] => 7/670246 [patent_app_country] => US [patent_app_date] => 1991-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 17 [patent_no_of_words] => 11506 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/270/05270979.pdf [firstpage_image] =>[orig_patent_app_number] => 670246 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2985811 [patent_doc_number] => 05257149 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-10-26 [patent_title] => 'Disc drive with offset address field' [patent_app_type] => 1 [patent_app_number] => 7/654900 [patent_app_country] => US [patent_app_date] => 1991-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 2483 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/257/05257149.pdf [firstpage_image] =>[orig_patent_app_number] => 654900 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2913276 [patent_doc_number] => 05249158 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-09-28 [patent_title] => 'Flash memory blocking architecture' [patent_app_type] => 1 [patent_app_number] => 7/654263 [patent_app_country] => US [patent_app_date] => 1991-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 5218 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 337 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/249/05249158.pdf [firstpage_image] =>[orig_patent_app_number] => 654263 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2978614 [patent_doc_number] => 05182472 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-01-26 [patent_title] => 'Logic circuit with bipolar CMOS configuration' [patent_app_type] => 1 [patent_app_number] => 7/651802 [patent_app_country] => US [patent_app_date] => 1991-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 5588 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 215 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/182/05182472.pdf [firstpage_image] =>[orig_patent_app_number] => 651802 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2739664 [patent_doc_number] => 05077490 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-12-31 [patent_title] => 'Schottky-diode emulator for BiCMOS logic circuit' [patent_app_type] => 1 [patent_app_number] => 7/647794 [patent_app_country] => US [patent_app_date] => 1991-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2255 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 300 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/077/05077490.pdf [firstpage_image] =>[orig_patent_app_number] => 647794 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2818457 [patent_doc_number] => 05122692 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-06-16 [patent_title] => 'High speed level conversion circuit including a switch circuit' [patent_app_type] => 1 [patent_app_number] => 7/645445 [patent_app_country] => US [patent_app_date] => 1991-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 2501 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/122/05122692.pdf [firstpage_image] =>[orig_patent_app_number] => 645445 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2777823 [patent_doc_number] => 05075578 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-12-24 [patent_title] => 'Input buffer regenerative latch' [patent_app_type] => 1 [patent_app_number] => 7/641983 [patent_app_country] => US [patent_app_date] => 1991-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1137 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/075/05075578.pdf [firstpage_image] =>[orig_patent_app_number] => 641983 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2793103 [patent_doc_number] => 05101124 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-03-31 [patent_title] => 'ECL to TTL translator circuit with improved slew rate' [patent_app_type] => 1 [patent_app_number] => 7/639793 [patent_app_country] => US [patent_app_date] => 1991-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2953 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 270 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/101/05101124.pdf [firstpage_image] =>[orig_patent_app_number] => 639793 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2684977 [patent_doc_number] => 05066876 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-11-19 [patent_title] => 'Circuit for converting ECL level signals to MOS level signals' [patent_app_type] => 1 [patent_app_number] => 7/632167 [patent_app_country] => US [patent_app_date] => 1990-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 2846 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 224 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/066/05066876.pdf [firstpage_image] =>[orig_patent_app_number] => 632167 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2788831 [patent_doc_number] => 05142168 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-08-25 [patent_title] => 'Emitter-coupled logic balanced signal transmission circuit' [patent_app_type] => 1 [patent_app_number] => 7/630061 [patent_app_country] => US [patent_app_date] => 1990-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2169 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/142/05142168.pdf [firstpage_image] =>[orig_patent_app_number] => 630061 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2863627 [patent_doc_number] => 05166551 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-11-24 [patent_title] => 'High speed output circuit without fluctuation for semiconductor integrated circuits' [patent_app_type] => 1 [patent_app_number] => 7/628906 [patent_app_country] => US [patent_app_date] => 1990-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 5963 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/166/05166551.pdf [firstpage_image] =>[orig_patent_app_number] => 628906 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2697885 [patent_doc_number] => 05065049 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-11-12 [patent_title] => 'MOS driver circuit having clamp means to hold the output voltage constant regardless of variations in the operating voltage' [patent_app_type] => 1 [patent_app_number] => 7/621829 [patent_app_country] => US [patent_app_date] => 1990-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 2598 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/065/05065049.pdf [firstpage_image] =>[orig_patent_app_number] => 621829 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2789968 [patent_doc_number] => 05130564 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-07-14 [patent_title] => 'Signal delay circuit for minimizing the delay time dependence on power supply voltage variation' [patent_app_type] => 1 [patent_app_number] => 7/620720 [patent_app_country] => US [patent_app_date] => 1990-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 34 [patent_no_of_words] => 3806 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 32 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/130/05130564.pdf [firstpage_image] =>[orig_patent_app_number] => 620720 [rel_patent_id] =>[rel_patent_doc_number] =>)