Search

David Lam

Examiner (ID: 2003, Phone: (571)272-1782 , Office: P/2825 )

Most Active Art Unit
2827
Art Unit(s)
2818, 2827, 2825
Total Applications
2102
Issued Applications
2016
Pending Applications
28
Abandoned Applications
60

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 12243350 [patent_doc_number] => 20180076212 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-03-15 [patent_title] => 'THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 15/805513 [patent_app_country] => US [patent_app_date] => 2017-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 30 [patent_no_of_words] => 12534 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15805513 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/805513
Three-dimensional semiconductor memory device including vertically stacked electrodes Nov 6, 2017 Issued
Array ( [id] => 13799051 [patent_doc_number] => 20190013064 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-01-10 [patent_title] => CIRCUITS FOR PULSE-WIDTH CONTROL IN MEMORY DEVICES AND RELATED METHODS [patent_app_type] => utility [patent_app_number] => 15/801733 [patent_app_country] => US [patent_app_date] => 2017-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4043 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15801733 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/801733
Circuits for pulse-width control in memory devices and related methods Nov 1, 2017 Issued
Array ( [id] => 14886977 [patent_doc_number] => 10423531 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-09-24 [patent_title] => Uninterrupted read of consecutive pages for memory [patent_app_type] => utility [patent_app_number] => 15/801148 [patent_app_country] => US [patent_app_date] => 2017-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7157 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15801148 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/801148
Uninterrupted read of consecutive pages for memory Oct 31, 2017 Issued
Array ( [id] => 14237597 [patent_doc_number] => 20190130971 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-05-02 [patent_title] => WRITE-TIME PREVENTION OF DATA RETENTION FAILURES FOR NON-VOLATILE MEMORY [patent_app_type] => utility [patent_app_number] => 15/800037 [patent_app_country] => US [patent_app_date] => 2017-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12153 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15800037 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/800037
WRITE-TIME PREVENTION OF DATA RETENTION FAILURES FOR NON-VOLATILE MEMORY Oct 30, 2017 Abandoned
Array ( [id] => 15015471 [patent_doc_number] => 10453896 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-10-22 [patent_title] => 4F2 resistive non-volatile memory formed in a NAND architecture [patent_app_type] => utility [patent_app_number] => 15/799261 [patent_app_country] => US [patent_app_date] => 2017-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 14648 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15799261 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/799261
4F2 resistive non-volatile memory formed in a NAND architecture Oct 30, 2017 Issued
Array ( [id] => 13320329 [patent_doc_number] => 20180211702 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-07-26 [patent_title] => SRAM WITH ACTIVE SUBSTRATE BIAS [patent_app_type] => utility [patent_app_number] => 15/782090 [patent_app_country] => US [patent_app_date] => 2017-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5663 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15782090 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/782090
Method and apparatus for controlling substrate and well biases for reduced power requirements Oct 11, 2017 Issued
Array ( [id] => 15108321 [patent_doc_number] => 10475490 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-11-12 [patent_title] => Memory devices with improved refreshing operation [patent_app_type] => utility [patent_app_number] => 15/728375 [patent_app_country] => US [patent_app_date] => 2017-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 3901 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15728375 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/728375
Memory devices with improved refreshing operation Oct 8, 2017 Issued
Array ( [id] => 14603847 [patent_doc_number] => 10355121 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-07-16 [patent_title] => 3D semiconductor device with stacked memory [patent_app_type] => utility [patent_app_number] => 15/727592 [patent_app_country] => US [patent_app_date] => 2017-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 133 [patent_figures_cnt] => 150 [patent_no_of_words] => 25076 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15727592 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/727592
3D semiconductor device with stacked memory Oct 6, 2017 Issued
Array ( [id] => 15286835 [patent_doc_number] => 10516089 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-12-24 [patent_title] => Memory cell comprising coupled Josephson junctions [patent_app_type] => utility [patent_app_number] => 15/726173 [patent_app_country] => US [patent_app_date] => 2017-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 38 [patent_figures_cnt] => 38 [patent_no_of_words] => 20360 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15726173 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/726173
Memory cell comprising coupled Josephson junctions Oct 4, 2017 Issued
Array ( [id] => 12140926 [patent_doc_number] => 20180019009 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-01-18 [patent_title] => 'BUFFERING SYSTEMS FOR ACCESSING MULTIPLE LAYERS OF MEMORY IN INTEGRATED CIRCUITS' [patent_app_type] => utility [patent_app_number] => 15/719300 [patent_app_country] => US [patent_app_date] => 2017-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 8103 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15719300 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/719300
BUFFERING SYSTEMS FOR ACCESSING MULTIPLE LAYERS OF MEMORY IN INTEGRATED CIRCUITS Sep 27, 2017 Abandoned
Array ( [id] => 13740099 [patent_doc_number] => 20180374519 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-12-27 [patent_title] => DISTRIBUTED GLOBAL-BITLINE KEEPER/PRECHARGE/HEADER CIRCUIT FOR CONTENTION FREE LOW VOLTAGE OPERATION IN 8T REGISTER FILES [patent_app_type] => utility [patent_app_number] => 15/716507 [patent_app_country] => US [patent_app_date] => 2017-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7080 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15716507 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/716507
Distributed global-bitline keeper/precharge/header circuit for low voltage operation Sep 25, 2017 Issued
Array ( [id] => 12122088 [patent_doc_number] => 20180005674 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-01-04 [patent_title] => 'DUAL MODE OPERATION HAVING POWER SAVING AND ACTIVE MODES IN A STACKED CIRCUIT TOPOLOGY WITH LOGIC PRESERVATION' [patent_app_type] => utility [patent_app_number] => 15/711135 [patent_app_country] => US [patent_app_date] => 2017-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5063 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15711135 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/711135
Dual mode operation having power saving and active modes in a stacked circuit topology with logic preservation Sep 20, 2017 Issued
Array ( [id] => 12262607 [patent_doc_number] => 20180081802 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-03-22 [patent_title] => 'HYBRID NON-VOLATILE MEMORY STRUCTURES AND METHODS THEREOF' [patent_app_type] => utility [patent_app_number] => 15/704011 [patent_app_country] => US [patent_app_date] => 2017-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4797 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15704011 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/704011
Hybrid non-volatile memory devices with static random access memory (SRAM) array and non-volatile memory (NVM) array Sep 13, 2017 Issued
Array ( [id] => 12848383 [patent_doc_number] => 20180174634 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-06-21 [patent_title] => MAGNETIC MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 15/700485 [patent_app_country] => US [patent_app_date] => 2017-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18581 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 210 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15700485 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/700485
Magnetic memory device Sep 10, 2017 Issued
Array ( [id] => 14252035 [patent_doc_number] => 10276224 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-04-30 [patent_title] => Magnetic memory having metal portions and magnetic memory array including same [patent_app_type] => utility [patent_app_number] => 15/700769 [patent_app_country] => US [patent_app_date] => 2017-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 30 [patent_no_of_words] => 11584 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 277 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15700769 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/700769
Magnetic memory having metal portions and magnetic memory array including same Sep 10, 2017 Issued
Array ( [id] => 14252079 [patent_doc_number] => 10276246 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-04-30 [patent_title] => Method and apparatus for enhancing the reliability of a non-volatile memory [patent_app_type] => utility [patent_app_number] => 15/701205 [patent_app_country] => US [patent_app_date] => 2017-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 11303 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 239 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15701205 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/701205
Method and apparatus for enhancing the reliability of a non-volatile memory Sep 10, 2017 Issued
Array ( [id] => 14332587 [patent_doc_number] => 10297317 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-05-21 [patent_title] => Non-volatile semiconductor memory device including clamp circuit with control transistor and amplifier circuit [patent_app_type] => utility [patent_app_number] => 15/694955 [patent_app_country] => US [patent_app_date] => 2017-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 14 [patent_no_of_words] => 5509 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 231 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15694955 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/694955
Non-volatile semiconductor memory device including clamp circuit with control transistor and amplifier circuit Sep 3, 2017 Issued
Array ( [id] => 12129065 [patent_doc_number] => 20180012651 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-01-11 [patent_title] => 'MEMORY ACCESS MODULE FOR PERFORMING MEMORY ACCESS MANAGEMENT' [patent_app_type] => utility [patent_app_number] => 15/679178 [patent_app_country] => US [patent_app_date] => 2017-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 10461 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15679178 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/679178
Memory access module for performing a plurality of sensing operations to generate digital values of a storage cell in order to perform decoding of the storage cell Aug 16, 2017 Issued
Array ( [id] => 14888617 [patent_doc_number] => 10424355 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-09-24 [patent_title] => Semiconductor integrated circuit including master chip and slave chip that are stacked [patent_app_type] => utility [patent_app_number] => 15/678662 [patent_app_country] => US [patent_app_date] => 2017-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6412 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15678662 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/678662
Semiconductor integrated circuit including master chip and slave chip that are stacked Aug 15, 2017 Issued
Array ( [id] => 12054263 [patent_doc_number] => 20170330606 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-11-16 [patent_title] => 'THREE-DIMENSIONAL SEMICONDUCTOR DEVICE WITH TOP DUMMY CELLS, BOTTOM DUMMY CELLS AND OPERATING METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 15/668102 [patent_app_country] => US [patent_app_date] => 2017-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5952 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15668102 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/668102
Semiconductor device and operating method thereof Aug 2, 2017 Issued
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