David Lam

Array ( [id] => 3962591 [patent_doc_number] => 05999479 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-07 [patent_title] => 'Row decoder for nonvolatile memory having a low-voltage power supply' [patent_app_type] => 1 [patent_app_number] => 9/010202 [patent_app_country] => US [patent_app_date] => 1998-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5282 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/999/05999479.pdf [firstpage_image] =>[orig_patent_app_number] => 010202 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3946955 [patent_doc_number] => 05940314 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-17 [patent_title] => 'Ultra-high density memory device' [patent_app_type] => 1 [patent_app_number] => 9/009304 [patent_app_country] => US [patent_app_date] => 1998-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 4972 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/940/05940314.pdf [firstpage_image] =>[orig_patent_app_number] => 009304 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3963809 [patent_doc_number] => 05978262 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-02 [patent_title] => 'Circuit and method of latching a bit line in a non-volatile memory' [patent_app_type] => 1 [patent_app_number] => 9/009290 [patent_app_country] => US [patent_app_date] => 1998-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 8143 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/978/05978262.pdf [firstpage_image] =>[orig_patent_app_number] => 009290 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3994127 [patent_doc_number] => 05949727 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-07 [patent_title] => 'Semiconductor memory device with data sensing scheme regardless of bit line coupling' [patent_app_type] => 1 [patent_app_number] => 9/006290 [patent_app_country] => US [patent_app_date] => 1998-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 5934 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/949/05949727.pdf [firstpage_image] =>[orig_patent_app_number] => 006290 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3960748 [patent_doc_number] => 05991229 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-23 [patent_title] => 'Internal clock generation circuit for synchronous semiconductor device' [patent_app_type] => 1 [patent_app_number] => 9/004000 [patent_app_country] => US [patent_app_date] => 1998-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 2900 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/991/05991229.pdf [firstpage_image] =>[orig_patent_app_number] => 004000 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4086464 [patent_doc_number] => 05966343 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-12 [patent_title] => 'Variable latency memory circuit' [patent_app_type] => 1 [patent_app_number] => 8/996522 [patent_app_country] => US [patent_app_date] => 1997-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 15 [patent_no_of_words] => 5277 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/966/05966343.pdf [firstpage_image] =>[orig_patent_app_number] => 996522 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4217115 [patent_doc_number] => 06078545 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-20 [patent_title] => 'Data transfer circuit' [patent_app_type] => 1 [patent_app_number] => 8/995520 [patent_app_country] => US [patent_app_date] => 1997-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4227 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/078/06078545.pdf [firstpage_image] =>[orig_patent_app_number] => 995520 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4284678 [patent_doc_number] => 06246602 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-12 [patent_title] => 'Ferroelectric storage device' [patent_app_type] => 1 [patent_app_number] => 8/995025 [patent_app_country] => US [patent_app_date] => 1997-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 14 [patent_no_of_words] => 8351 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/246/06246602.pdf [firstpage_image] =>[orig_patent_app_number] => 995025 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3950360 [patent_doc_number] => 05930163 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-27 [patent_title] => 'Semiconductor memory device having two P-well layout structure' [patent_app_type] => 1 [patent_app_number] => 8/993180 [patent_app_country] => US [patent_app_date] => 1997-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 22 [patent_no_of_words] => 5009 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 208 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/930/05930163.pdf [firstpage_image] =>[orig_patent_app_number] => 993180 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3960193 [patent_doc_number] => 05991196 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-23 [patent_title] => 'Reprogrammable memory device with variable page size' [patent_app_type] => 1 [patent_app_number] => 8/991423 [patent_app_country] => US [patent_app_date] => 1997-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2994 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/991/05991196.pdf [firstpage_image] =>[orig_patent_app_number] => 991423 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3925293 [patent_doc_number] => 06002625 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-14 [patent_title] => 'Cell array and sense amplifier structure exhibiting improved noise characteristic and reduced size' [patent_app_type] => 1 [patent_app_number] => 8/991618 [patent_app_country] => US [patent_app_date] => 1997-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 21 [patent_no_of_words] => 3737 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/002/06002625.pdf [firstpage_image] =>[orig_patent_app_number] => 991618 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3932542 [patent_doc_number] => 05914897 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-06-22 [patent_title] => 'FIFO memory device having address detection portion' [patent_app_type] => 1 [patent_app_number] => 8/990801 [patent_app_country] => US [patent_app_date] => 1997-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 4754 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/914/05914897.pdf [firstpage_image] =>[orig_patent_app_number] => 990801 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4054487 [patent_doc_number] => 05875131 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-02-23 [patent_title] => 'Presettable static ram with read/write controller' [patent_app_type] => 1 [patent_app_number] => 8/988100 [patent_app_country] => US [patent_app_date] => 1997-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 18 [patent_no_of_words] => 3261 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/875/05875131.pdf [firstpage_image] =>[orig_patent_app_number] => 988100 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4054586 [patent_doc_number] => 05912851 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-06-15 [patent_title] => 'Multi-bit semiconductor memory device allowing efficient testing' [patent_app_type] => 1 [patent_app_number] => 8/988208 [patent_app_country] => US [patent_app_date] => 1997-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 31 [patent_no_of_words] => 17091 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/912/05912851.pdf [firstpage_image] =>[orig_patent_app_number] => 988208 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3950402 [patent_doc_number] => 05930166 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-27 [patent_title] => 'Semiconductor memory device with triple metal layer' [patent_app_type] => 1 [patent_app_number] => 8/986905 [patent_app_country] => US [patent_app_date] => 1997-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1635 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/930/05930166.pdf [firstpage_image] =>[orig_patent_app_number] => 986905 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3853970 [patent_doc_number] => 05848026 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-12-08 [patent_title] => 'Integrated circuit with flag register for block selection of nonvolatile cells for bulk operations' [patent_app_type] => 1 [patent_app_number] => 8/986506 [patent_app_country] => US [patent_app_date] => 1997-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 5409 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/848/05848026.pdf [firstpage_image] =>[orig_patent_app_number] => 986506 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3950754 [patent_doc_number] => 05930191 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-27 [patent_title] => 'Semiconductor memory device having a plurality of power voltages' [patent_app_type] => 1 [patent_app_number] => 8/986908 [patent_app_country] => US [patent_app_date] => 1997-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1620 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/930/05930191.pdf [firstpage_image] =>[orig_patent_app_number] => 986908 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4046028 [patent_doc_number] => 05943283 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-24 [patent_title] => 'Address scrambling in a semiconductor memory' [patent_app_type] => 1 [patent_app_number] => 8/986210 [patent_app_country] => US [patent_app_date] => 1997-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 6064 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/943/05943283.pdf [firstpage_image] =>[orig_patent_app_number] => 986210 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4054359 [patent_doc_number] => 05912836 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-06-15 [patent_title] => 'Circuit for detecting both charge gain and charge loss properties in a non-volatile memory array' [patent_app_type] => 1 [patent_app_number] => 8/982204 [patent_app_country] => US [patent_app_date] => 1997-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 3883 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/912/05912836.pdf [firstpage_image] =>[orig_patent_app_number] => 982204 [rel_patent_id] =>[rel_patent_doc_number] =>)