Search

David Lam

Examiner (ID: 14034, Phone: (571)272-1782 , Office: P/2825 )

Most Active Art Unit
2827
Art Unit(s)
2825, 2827, 2818
Total Applications
2102
Issued Applications
2016
Pending Applications
28
Abandoned Applications
60

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4078048 [patent_doc_number] => 06009021 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-28 [patent_title] => 'MOS logic circuit with hold operation' [patent_app_type] => 1 [patent_app_number] => 8/956541 [patent_app_country] => US [patent_app_date] => 1997-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 21 [patent_no_of_words] => 6599 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/009/06009021.pdf [firstpage_image] =>[orig_patent_app_number] => 956541 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/956541
MOS logic circuit with hold operation Oct 22, 1997 Issued
Array ( [id] => 3952815 [patent_doc_number] => 05990700 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-23 [patent_title] => 'Input buffer circuit and method' [patent_app_type] => 1 [patent_app_number] => 8/955567 [patent_app_country] => US [patent_app_date] => 1997-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 9 [patent_no_of_words] => 1738 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/990/05990700.pdf [firstpage_image] =>[orig_patent_app_number] => 955567 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/955567
Input buffer circuit and method Oct 21, 1997 Issued
Array ( [id] => 3770408 [patent_doc_number] => 05852573 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-12-22 [patent_title] => 'Polyload sram memory cell with low stanby current' [patent_app_type] => 1 [patent_app_number] => 8/946827 [patent_app_country] => US [patent_app_date] => 1997-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 1961 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 225 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/852/05852573.pdf [firstpage_image] =>[orig_patent_app_number] => 946827 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/946827
Polyload sram memory cell with low stanby current Oct 7, 1997 Issued
Array ( [id] => 3953022 [patent_doc_number] => 05973949 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-26 [patent_title] => 'Input structure for analog or digital associative memories' [patent_app_type] => 1 [patent_app_number] => 8/941879 [patent_app_country] => US [patent_app_date] => 1997-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 2294 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/973/05973949.pdf [firstpage_image] =>[orig_patent_app_number] => 941879 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/941879
Input structure for analog or digital associative memories Sep 29, 1997 Issued
Array ( [id] => 3937091 [patent_doc_number] => 05946235 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-31 [patent_title] => 'Floating gate MOS transistor charge injection circuit and computation devices incorporating it' [patent_app_type] => 1 [patent_app_number] => 8/940278 [patent_app_country] => US [patent_app_date] => 1997-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3080 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/946/05946235.pdf [firstpage_image] =>[orig_patent_app_number] => 940278 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/940278
Floating gate MOS transistor charge injection circuit and computation devices incorporating it Sep 29, 1997 Issued
Array ( [id] => 4011840 [patent_doc_number] => 05986922 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-16 [patent_title] => 'Method of and apparatus for increasing load resistance within an SRAM array' [patent_app_type] => 1 [patent_app_number] => 8/941582 [patent_app_country] => US [patent_app_date] => 1997-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 2439 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/986/05986922.pdf [firstpage_image] =>[orig_patent_app_number] => 941582 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/941582
Method of and apparatus for increasing load resistance within an SRAM array Sep 29, 1997 Issued
Array ( [id] => 3970934 [patent_doc_number] => 05901085 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-05-04 [patent_title] => 'Programmable reference voltage source, particularly for analog memories' [patent_app_type] => 1 [patent_app_number] => 8/941880 [patent_app_country] => US [patent_app_date] => 1997-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3434 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/901/05901085.pdf [firstpage_image] =>[orig_patent_app_number] => 941880 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/941880
Programmable reference voltage source, particularly for analog memories Sep 29, 1997 Issued
Array ( [id] => 3986358 [patent_doc_number] => 05905669 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-05-18 [patent_title] => 'Hierarchical routing method to be implemented in a layout system for a semiconductor integrated circuit and medium on which the hierarchical routing program is stored' [patent_app_type] => 1 [patent_app_number] => 8/940005 [patent_app_country] => US [patent_app_date] => 1997-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 13 [patent_no_of_words] => 5728 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/905/05905669.pdf [firstpage_image] =>[orig_patent_app_number] => 940005 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/940005
Hierarchical routing method to be implemented in a layout system for a semiconductor integrated circuit and medium on which the hierarchical routing program is stored Sep 28, 1997 Issued
Array ( [id] => 3940243 [patent_doc_number] => 05953265 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-14 [patent_title] => 'Memory having error detection and correction' [patent_app_type] => 1 [patent_app_number] => 8/941509 [patent_app_country] => US [patent_app_date] => 1997-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 3639 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 13 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/953/05953265.pdf [firstpage_image] =>[orig_patent_app_number] => 941509 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/941509
Memory having error detection and correction Sep 28, 1997 Issued
Array ( [id] => 3950666 [patent_doc_number] => 05930185 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-27 [patent_title] => 'Data retention test for static memory cell' [patent_app_type] => 1 [patent_app_number] => 8/938732 [patent_app_country] => US [patent_app_date] => 1997-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 27 [patent_no_of_words] => 17560 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/930/05930185.pdf [firstpage_image] =>[orig_patent_app_number] => 938732 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/938732
Data retention test for static memory cell Sep 25, 1997 Issued
Array ( [id] => 3905063 [patent_doc_number] => 05835418 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-11-10 [patent_title] => 'Input/output buffer memory circuit capable of minimizing data transfer required in input and output buffering operations' [patent_app_type] => 1 [patent_app_number] => 8/938839 [patent_app_country] => US [patent_app_date] => 1997-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 7000 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 214 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/835/05835418.pdf [firstpage_image] =>[orig_patent_app_number] => 938839 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/938839
Input/output buffer memory circuit capable of minimizing data transfer required in input and output buffering operations Sep 25, 1997 Issued
Array ( [id] => 4077841 [patent_doc_number] => 05867444 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-02-02 [patent_title] => 'Programmable memory device that supports multiple operational modes' [patent_app_type] => 1 [patent_app_number] => 8/937535 [patent_app_country] => US [patent_app_date] => 1997-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 4822 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/867/05867444.pdf [firstpage_image] =>[orig_patent_app_number] => 937535 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/937535
Programmable memory device that supports multiple operational modes Sep 24, 1997 Issued
Array ( [id] => 4054376 [patent_doc_number] => 05909397 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-06-01 [patent_title] => 'Method and system for testing and adjusting threshold voltages in flash eeproms' [patent_app_type] => 1 [patent_app_number] => 8/935240 [patent_app_country] => US [patent_app_date] => 1997-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 3714 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/909/05909397.pdf [firstpage_image] =>[orig_patent_app_number] => 935240 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/935240
Method and system for testing and adjusting threshold voltages in flash eeproms Sep 21, 1997 Issued
Array ( [id] => 3775131 [patent_doc_number] => 05844857 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-12-01 [patent_title] => 'Row address control circuits having a predecoding address sampling pulse generator and methods for memory devices' [patent_app_type] => 1 [patent_app_number] => 8/934434 [patent_app_country] => US [patent_app_date] => 1997-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 4385 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/844/05844857.pdf [firstpage_image] =>[orig_patent_app_number] => 934434 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/934434
Row address control circuits having a predecoding address sampling pulse generator and methods for memory devices Sep 18, 1997 Issued
Array ( [id] => 4064313 [patent_doc_number] => 05933375 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-03 [patent_title] => 'Main amplifier with fast output disablement' [patent_app_type] => 1 [patent_app_number] => 8/932384 [patent_app_country] => US [patent_app_date] => 1997-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 3614 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/933/05933375.pdf [firstpage_image] =>[orig_patent_app_number] => 932384 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/932384
Main amplifier with fast output disablement Sep 16, 1997 Issued
Array ( [id] => 4065380 [patent_doc_number] => 05970017 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-19 [patent_title] => 'Decode circuit for use in semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 8/932178 [patent_app_country] => US [patent_app_date] => 1997-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5606 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/970/05970017.pdf [firstpage_image] =>[orig_patent_app_number] => 932178 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/932178
Decode circuit for use in semiconductor memory device Sep 16, 1997 Issued
Array ( [id] => 3940531 [patent_doc_number] => 05953285 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-14 [patent_title] => 'Scan path circuitry including an output register having a flow through mode' [patent_app_type] => 1 [patent_app_number] => 8/932638 [patent_app_country] => US [patent_app_date] => 1997-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 16 [patent_no_of_words] => 11676 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/953/05953285.pdf [firstpage_image] =>[orig_patent_app_number] => 932638 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/932638
Scan path circuitry including an output register having a flow through mode Sep 16, 1997 Issued
Array ( [id] => 3988851 [patent_doc_number] => 05917772 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-06-29 [patent_title] => 'Data input circuit for eliminating idle cycles in a memory device' [patent_app_type] => 1 [patent_app_number] => 8/931779 [patent_app_country] => US [patent_app_date] => 1997-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 14 [patent_no_of_words] => 6533 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/917/05917772.pdf [firstpage_image] =>[orig_patent_app_number] => 931779 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/931779
Data input circuit for eliminating idle cycles in a memory device Sep 15, 1997 Issued
Array ( [id] => 3816155 [patent_doc_number] => 05854772 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-12-29 [patent_title] => 'Decoder circuit with less transistor elements' [patent_app_type] => 1 [patent_app_number] => 8/925738 [patent_app_country] => US [patent_app_date] => 1997-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 8077 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 219 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/854/05854772.pdf [firstpage_image] =>[orig_patent_app_number] => 925738 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/925738
Decoder circuit with less transistor elements Sep 8, 1997 Issued
Array ( [id] => 4054560 [patent_doc_number] => 05875134 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-02-23 [patent_title] => 'Data communication for memory' [patent_app_type] => 1 [patent_app_number] => 8/925934 [patent_app_country] => US [patent_app_date] => 1997-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 25 [patent_no_of_words] => 7109 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/875/05875134.pdf [firstpage_image] =>[orig_patent_app_number] => 925934 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/925934
Data communication for memory Sep 7, 1997 Issued
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