Search

David Lam

Examiner (ID: 14034, Phone: (571)272-1782 , Office: P/2825 )

Most Active Art Unit
2827
Art Unit(s)
2825, 2827, 2818
Total Applications
2102
Issued Applications
2016
Pending Applications
28
Abandoned Applications
60

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4034340 [patent_doc_number] => 05926409 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-20 [patent_title] => 'Method and apparatus for an adaptive ramp amplitude controller in nonvolatile memory application' [patent_app_type] => 1 [patent_app_number] => 8/924284 [patent_app_country] => US [patent_app_date] => 1997-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 5091 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/926/05926409.pdf [firstpage_image] =>[orig_patent_app_number] => 924284 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/924284
Method and apparatus for an adaptive ramp amplitude controller in nonvolatile memory application Sep 4, 1997 Issued
Array ( [id] => 4196957 [patent_doc_number] => 06160733 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-12 [patent_title] => 'Low voltage and low power static random access memory (SRAM)' [patent_app_type] => 1 [patent_app_number] => 8/920682 [patent_app_country] => US [patent_app_date] => 1997-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 8165 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/160/06160733.pdf [firstpage_image] =>[orig_patent_app_number] => 920682 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/920682
Low voltage and low power static random access memory (SRAM) Aug 28, 1997 Issued
Array ( [id] => 3937385 [patent_doc_number] => 05946256 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-31 [patent_title] => 'Semiconductor memory having data transfer between RAM array and SAM array' [patent_app_type] => 1 [patent_app_number] => 8/920907 [patent_app_country] => US [patent_app_date] => 1997-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3819 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/946/05946256.pdf [firstpage_image] =>[orig_patent_app_number] => 920907 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/920907
Semiconductor memory having data transfer between RAM array and SAM array Aug 28, 1997 Issued
Array ( [id] => 3853865 [patent_doc_number] => 05848019 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-12-08 [patent_title] => 'Pass gate decoder for a multiport memory dEvice that uses a single ported memory cell array structure' [patent_app_type] => 1 [patent_app_number] => 8/920737 [patent_app_country] => US [patent_app_date] => 1997-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2565 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 233 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/848/05848019.pdf [firstpage_image] =>[orig_patent_app_number] => 920737 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/920737
Pass gate decoder for a multiport memory dEvice that uses a single ported memory cell array structure Aug 28, 1997 Issued
Array ( [id] => 3845739 [patent_doc_number] => 05815451 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-29 [patent_title] => 'Dynamic semiconductor memory device having a precharge circuit using low power consumption' [patent_app_type] => 1 [patent_app_number] => 8/919240 [patent_app_country] => US [patent_app_date] => 1997-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 7183 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 226 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/815/05815451.pdf [firstpage_image] =>[orig_patent_app_number] => 919240 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/919240
Dynamic semiconductor memory device having a precharge circuit using low power consumption Aug 27, 1997 Issued
Array ( [id] => 3802678 [patent_doc_number] => 05841720 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-11-24 [patent_title] => 'Folded dummy world line' [patent_app_type] => 1 [patent_app_number] => 8/918740 [patent_app_country] => US [patent_app_date] => 1997-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2538 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/841/05841720.pdf [firstpage_image] =>[orig_patent_app_number] => 918740 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/918740
Folded dummy world line Aug 25, 1997 Issued
Array ( [id] => 3970814 [patent_doc_number] => 05901077 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-05-04 [patent_title] => 'Semiconductor memory device comprising ferroelectric capacitors' [patent_app_type] => 1 [patent_app_number] => 8/918538 [patent_app_country] => US [patent_app_date] => 1997-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 18 [patent_no_of_words] => 6738 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/901/05901077.pdf [firstpage_image] =>[orig_patent_app_number] => 918538 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/918538
Semiconductor memory device comprising ferroelectric capacitors Aug 21, 1997 Issued
Array ( [id] => 3937399 [patent_doc_number] => 05946257 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-31 [patent_title] => 'Selective power distribution circuit for an integrated circuit' [patent_app_type] => 1 [patent_app_number] => 8/918637 [patent_app_country] => US [patent_app_date] => 1997-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 6838 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/946/05946257.pdf [firstpage_image] =>[orig_patent_app_number] => 918637 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/918637
Selective power distribution circuit for an integrated circuit Aug 21, 1997 Issued
Array ( [id] => 3915577 [patent_doc_number] => 05898639 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-04-27 [patent_title] => 'Memory with variable write driver operation' [patent_app_type] => 1 [patent_app_number] => 8/918635 [patent_app_country] => US [patent_app_date] => 1997-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 3111 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/898/05898639.pdf [firstpage_image] =>[orig_patent_app_number] => 918635 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/918635
Memory with variable write driver operation Aug 21, 1997 Issued
Array ( [id] => 3971060 [patent_doc_number] => 05901092 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-05-04 [patent_title] => 'Memory device having pipelined access and method for pipelining data access' [patent_app_type] => 1 [patent_app_number] => 8/917036 [patent_app_country] => US [patent_app_date] => 1997-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 3851 [patent_no_of_claims] => 41 [patent_no_of_ind_claims] => 12 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/901/05901092.pdf [firstpage_image] =>[orig_patent_app_number] => 917036 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/917036
Memory device having pipelined access and method for pipelining data access Aug 21, 1997 Issued
Array ( [id] => 4045548 [patent_doc_number] => 05856940 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-01-05 [patent_title] => 'Low latency DRAM cell and method therefor' [patent_app_type] => 1 [patent_app_number] => 8/911737 [patent_app_country] => US [patent_app_date] => 1997-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 11 [patent_no_of_words] => 6926 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/856/05856940.pdf [firstpage_image] =>[orig_patent_app_number] => 911737 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/911737
Low latency DRAM cell and method therefor Aug 14, 1997 Issued
Array ( [id] => 4077915 [patent_doc_number] => 05867449 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-02-02 [patent_title] => 'Tracking signals' [patent_app_type] => 1 [patent_app_number] => 8/911329 [patent_app_country] => US [patent_app_date] => 1997-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3306 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/867/05867449.pdf [firstpage_image] =>[orig_patent_app_number] => 911329 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/911329
Tracking signals Aug 13, 1997 Issued
Array ( [id] => 3821099 [patent_doc_number] => 05831895 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-11-03 [patent_title] => 'Dynamic cell plate sensing and equilibration in a memory device' [patent_app_type] => 1 [patent_app_number] => 8/903541 [patent_app_country] => US [patent_app_date] => 1997-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3232 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/831/05831895.pdf [firstpage_image] =>[orig_patent_app_number] => 903541 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/903541
Dynamic cell plate sensing and equilibration in a memory device Jul 29, 1997 Issued
Array ( [id] => 4037184 [patent_doc_number] => 05883846 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-16 [patent_title] => 'Latch type sense amplifier having a negative feedback device' [patent_app_type] => 1 [patent_app_number] => 8/901627 [patent_app_country] => US [patent_app_date] => 1997-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 15 [patent_no_of_words] => 4465 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/883/05883846.pdf [firstpage_image] =>[orig_patent_app_number] => 901627 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/901627
Latch type sense amplifier having a negative feedback device Jul 27, 1997 Issued
Array ( [id] => 3939844 [patent_doc_number] => 05877988 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-02 [patent_title] => 'Read/write control circuit for semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 8/901433 [patent_app_country] => US [patent_app_date] => 1997-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 21 [patent_no_of_words] => 2618 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/877/05877988.pdf [firstpage_image] =>[orig_patent_app_number] => 901433 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/901433
Read/write control circuit for semiconductor memory device Jul 24, 1997 Issued
Array ( [id] => 4126912 [patent_doc_number] => 06046945 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-04-04 [patent_title] => 'DRAM repair apparatus and method' [patent_app_type] => 1 [patent_app_number] => 8/890696 [patent_app_country] => US [patent_app_date] => 1997-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 2478 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/046/06046945.pdf [firstpage_image] =>[orig_patent_app_number] => 890696 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/890696
DRAM repair apparatus and method Jul 10, 1997 Issued
Array ( [id] => 3896233 [patent_doc_number] => 05894432 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-04-13 [patent_title] => 'CMOS memory cell with improved read port' [patent_app_type] => 1 [patent_app_number] => 8/889728 [patent_app_country] => US [patent_app_date] => 1997-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2821 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/894/05894432.pdf [firstpage_image] =>[orig_patent_app_number] => 889728 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/889728
CMOS memory cell with improved read port Jul 7, 1997 Issued
Array ( [id] => 4093779 [patent_doc_number] => 06055211 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-04-25 [patent_title] => 'Force page zero paging scheme for microcontrollers using data random access memory' [patent_app_type] => 1 [patent_app_number] => 8/887876 [patent_app_country] => US [patent_app_date] => 1997-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 1663 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/055/06055211.pdf [firstpage_image] =>[orig_patent_app_number] => 887876 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/887876
Force page zero paging scheme for microcontrollers using data random access memory Jul 2, 1997 Issued
Array ( [id] => 3853957 [patent_doc_number] => 05848025 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-12-08 [patent_title] => 'Method and apparatus for controlling a memory device in a page mode' [patent_app_type] => 1 [patent_app_number] => 8/885434 [patent_app_country] => US [patent_app_date] => 1997-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 3286 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/848/05848025.pdf [firstpage_image] =>[orig_patent_app_number] => 885434 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/885434
Method and apparatus for controlling a memory device in a page mode Jun 29, 1997 Issued
Array ( [id] => 4037238 [patent_doc_number] => 05883849 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-16 [patent_title] => 'Method and apparatus for simultaneous memory subarray testing' [patent_app_type] => 1 [patent_app_number] => 8/885535 [patent_app_country] => US [patent_app_date] => 1997-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2001 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/883/05883849.pdf [firstpage_image] =>[orig_patent_app_number] => 885535 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/885535
Method and apparatus for simultaneous memory subarray testing Jun 29, 1997 Issued
Menu