Search

David Lam

Examiner (ID: 2003, Phone: (571)272-1782 , Office: P/2825 )

Most Active Art Unit
2827
Art Unit(s)
2818, 2827, 2825
Total Applications
2102
Issued Applications
2016
Pending Applications
28
Abandoned Applications
60

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 14558351 [patent_doc_number] => 10347646 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-07-09 [patent_title] => Anti-fuse cell structure including reading and programming devices with different gate dielectric thickness [patent_app_type] => utility [patent_app_number] => 15/649096 [patent_app_country] => US [patent_app_date] => 2017-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 38 [patent_no_of_words] => 5891 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15649096 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/649096
Anti-fuse cell structure including reading and programming devices with different gate dielectric thickness Jul 12, 2017 Issued
Array ( [id] => 12005162 [patent_doc_number] => 20170309317 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-10-26 [patent_title] => 'RECEPTION CIRCUIT AND ELECTRONIC APPARATUS INCLUDING THE SAME' [patent_app_type] => utility [patent_app_number] => 15/649152 [patent_app_country] => US [patent_app_date] => 2017-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4099 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15649152 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/649152
Reception circuit for reducing current and electronic apparatus including the same Jul 12, 2017 Issued
Array ( [id] => 15169511 [patent_doc_number] => 10490258 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-11-26 [patent_title] => Semiconductor device with stacked structure of memory cells over sensing amplifiers, circuit board and electronic device [patent_app_type] => utility [patent_app_number] => 15/644905 [patent_app_country] => US [patent_app_date] => 2017-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 64 [patent_no_of_words] => 26447 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15644905 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/644905
Semiconductor device with stacked structure of memory cells over sensing amplifiers, circuit board and electronic device Jul 9, 2017 Issued
Array ( [id] => 12101910 [patent_doc_number] => 09859009 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-01-02 [patent_title] => 'Semiconductor memory device for switching high voltage without potential drop' [patent_app_type] => utility [patent_app_number] => 15/630018 [patent_app_country] => US [patent_app_date] => 2017-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 8198 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15630018 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/630018
Semiconductor memory device for switching high voltage without potential drop Jun 21, 2017 Issued
Array ( [id] => 12195357 [patent_doc_number] => 09899091 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-02-20 [patent_title] => 'Semiconductor memory device for switching high voltage without potential drop' [patent_app_type] => utility [patent_app_number] => 15/629987 [patent_app_country] => US [patent_app_date] => 2017-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 8201 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15629987 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/629987
Semiconductor memory device for switching high voltage without potential drop Jun 21, 2017 Issued
Array ( [id] => 12140925 [patent_doc_number] => 20180019008 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-01-18 [patent_title] => 'BUFFERING SYSTEMS FOR ACCESSING MULTIPLE LAYERS OF MEMORY IN INTEGRATED CIRCUITS' [patent_app_type] => utility [patent_app_number] => 15/623163 [patent_app_country] => US [patent_app_date] => 2017-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 8082 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15623163 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/623163
BUFFERING SYSTEMS FOR ACCESSING MULTIPLE LAYERS OF MEMORY IN INTEGRATED CIRCUITS Jun 13, 2017 Abandoned
Array ( [id] => 11952155 [patent_doc_number] => 20170256306 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-09-07 [patent_title] => 'Memory Array with Bit-Lines Connected to Different Sub-Arrays Through Jumper Structures' [patent_app_type] => utility [patent_app_number] => 15/601445 [patent_app_country] => US [patent_app_date] => 2017-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5589 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15601445 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/601445
Memory array with bit-lines connected to different sub-arrays through jumper structures May 21, 2017 Issued
Array ( [id] => 12174636 [patent_doc_number] => 09892783 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-02-13 [patent_title] => 'Non-volatile memory device including memory cells having variable resistance values' [patent_app_type] => utility [patent_app_number] => 15/593333 [patent_app_country] => US [patent_app_date] => 2017-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 27 [patent_no_of_words] => 18056 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15593333 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/593333
Non-volatile memory device including memory cells having variable resistance values May 11, 2017 Issued
Array ( [id] => 14429225 [patent_doc_number] => 10319426 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-06-11 [patent_title] => Semiconductor structures, memory cells and devices comprising ferroelectric materials, systems including same, and related methods [patent_app_type] => utility [patent_app_number] => 15/590863 [patent_app_country] => US [patent_app_date] => 2017-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 7274 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15590863 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/590863
Semiconductor structures, memory cells and devices comprising ferroelectric materials, systems including same, and related methods May 8, 2017 Issued
Array ( [id] => 14011281 [patent_doc_number] => 10224115 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-03-05 [patent_title] => Self-repair logic for stacked memory architecture [patent_app_type] => utility [patent_app_number] => 15/589308 [patent_app_country] => US [patent_app_date] => 2017-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6792 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15589308 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/589308
Self-repair logic for stacked memory architecture May 7, 2017 Issued
Array ( [id] => 12313842 [patent_doc_number] => 09940999 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-04-10 [patent_title] => Semiconductor devices, circuits and methods for read and/or write assist of an SRAM circuit portion based on voltage detection and/or temperature detection circuits [patent_app_type] => utility [patent_app_number] => 15/587947 [patent_app_country] => US [patent_app_date] => 2017-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 33 [patent_no_of_words] => 17247 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15587947 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/587947
Semiconductor devices, circuits and methods for read and/or write assist of an SRAM circuit portion based on voltage detection and/or temperature detection circuits May 4, 2017 Issued
Array ( [id] => 12122115 [patent_doc_number] => 20180005700 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-01-04 [patent_title] => 'OPERATION METHOD OF NONVOLATILE MEMORY SYSTEM AND OPERATION METHOD OF NONVOLATILE MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 15/587461 [patent_app_country] => US [patent_app_date] => 2017-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 10667 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15587461 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/587461
Operation method of nonvolatile memory system that includes erase operations, fast erase operations, program operations and fast program operations May 4, 2017 Issued
Array ( [id] => 12202222 [patent_doc_number] => 09905294 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-02-27 [patent_title] => 'Writing logically offset pages of data to N-level memory cells coupled to a common word line' [patent_app_type] => utility [patent_app_number] => 15/585429 [patent_app_country] => US [patent_app_date] => 2017-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 15 [patent_no_of_words] => 6275 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15585429 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/585429
Writing logically offset pages of data to N-level memory cells coupled to a common word line May 2, 2017 Issued
Array ( [id] => 13694807 [patent_doc_number] => 20170358358 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-12-14 [patent_title] => FLASH MEMORY [patent_app_type] => utility [patent_app_number] => 15/585871 [patent_app_country] => US [patent_app_date] => 2017-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6879 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15585871 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/585871
FLASH MEMORY May 2, 2017 Abandoned
Array ( [id] => 14035997 [patent_doc_number] => 10229751 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-03-12 [patent_title] => Storage system and method for bad block recycling [patent_app_type] => utility [patent_app_number] => 15/583747 [patent_app_country] => US [patent_app_date] => 2017-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 6515 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15583747 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/583747
Storage system and method for bad block recycling Apr 30, 2017 Issued
Array ( [id] => 13527867 [patent_doc_number] => 20180315476 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-11-01 [patent_title] => MOLECULAR MULTIPLE QUANTUM BIT, QUANTUM STORAGE DEVICE AND MOLECULAR QUANTUM COMPUTER [patent_app_type] => utility [patent_app_number] => 15/582779 [patent_app_country] => US [patent_app_date] => 2017-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3505 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15582779 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/582779
Molecular quantum computer and molecular quantum storage device Apr 30, 2017 Issued
Array ( [id] => 12202218 [patent_doc_number] => 09905289 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-02-27 [patent_title] => 'Method and system for systematic read retry flow in solid state memory' [patent_app_type] => utility [patent_app_number] => 15/581101 [patent_app_country] => US [patent_app_date] => 2017-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 15 [patent_no_of_words] => 10001 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 278 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15581101 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/581101
Method and system for systematic read retry flow in solid state memory Apr 27, 2017 Issued
Array ( [id] => 12435795 [patent_doc_number] => 09978447 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-05-22 [patent_title] => Memory cell with improved write margin [patent_app_type] => utility [patent_app_number] => 15/496655 [patent_app_country] => US [patent_app_date] => 2017-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 9270 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 45 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15496655 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/496655
Memory cell with improved write margin Apr 24, 2017 Issued
Array ( [id] => 14459361 [patent_doc_number] => 10325651 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-06-18 [patent_title] => 3D semiconductor device with stacked memory [patent_app_type] => utility [patent_app_number] => 15/494525 [patent_app_country] => US [patent_app_date] => 2017-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 43 [patent_figures_cnt] => 44 [patent_no_of_words] => 9565 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15494525 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/494525
3D semiconductor device with stacked memory Apr 22, 2017 Issued
Array ( [id] => 12477252 [patent_doc_number] => 09991003 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-06-05 [patent_title] => Methods for reading and operating memory device including efuse [patent_app_type] => utility [patent_app_number] => 15/492531 [patent_app_country] => US [patent_app_date] => 2017-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 9290 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 290 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15492531 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/492531
Methods for reading and operating memory device including efuse Apr 19, 2017 Issued
Menu