Search

David Lam

Examiner (ID: 9276, Phone: (571)272-1782 , Office: P/2825 )

Most Active Art Unit
2827
Art Unit(s)
2818, 2825, 2827
Total Applications
2102
Issued Applications
2016
Pending Applications
28
Abandoned Applications
60

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 12477252 [patent_doc_number] => 09991003 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-06-05 [patent_title] => Methods for reading and operating memory device including efuse [patent_app_type] => utility [patent_app_number] => 15/492531 [patent_app_country] => US [patent_app_date] => 2017-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 9290 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 290 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15492531 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/492531
Methods for reading and operating memory device including efuse Apr 19, 2017 Issued
Array ( [id] => 12534186 [patent_doc_number] => 10008252 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-06-26 [patent_title] => Semiconductor system capable of storing different setting information in plurality of semiconductor chips sharing command/address information [patent_app_type] => utility [patent_app_number] => 15/477619 [patent_app_country] => US [patent_app_date] => 2017-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 19 [patent_no_of_words] => 16873 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15477619 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/477619
Semiconductor system capable of storing different setting information in plurality of semiconductor chips sharing command/address information Apr 2, 2017 Issued
Array ( [id] => 12534168 [patent_doc_number] => 10008246 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-06-26 [patent_title] => Memory and reference circuit calibration method thereof [patent_app_type] => utility [patent_app_number] => 15/477215 [patent_app_country] => US [patent_app_date] => 2017-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 6846 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15477215 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/477215
Memory and reference circuit calibration method thereof Apr 2, 2017 Issued
Array ( [id] => 13470663 [patent_doc_number] => 20180286874 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-10-04 [patent_title] => CONDUCTIVE CHANNELS AND SOURCE LINE COUPLING [patent_app_type] => utility [patent_app_number] => 15/477051 [patent_app_country] => US [patent_app_date] => 2017-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9117 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -27 [patent_words_short_claim] => 46 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15477051 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/477051
Non-volatile memory structures having multi-layer conductive channels Mar 31, 2017 Issued
Array ( [id] => 12223134 [patent_doc_number] => 20180061495 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-03-01 [patent_title] => 'LEVEL SHIFTER CIRCUIT' [patent_app_type] => utility [patent_app_number] => 15/476003 [patent_app_country] => US [patent_app_date] => 2017-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5252 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15476003 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/476003
Level shifter circuit and associated memory device Mar 30, 2017 Issued
Array ( [id] => 12609891 [patent_doc_number] => 20180095127 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-04-05 [patent_title] => SYSTEMS, METHODS, AND APPARATUSES FOR IMPLEMENTING TESTING OF FAULT REPAIRS TO A THROUGH SILICON VIA (TSV) IN TWO-LEVEL MEMORY (2LM) STACKED DIE SUBSYSTEMS [patent_app_type] => utility [patent_app_number] => 15/475892 [patent_app_country] => US [patent_app_date] => 2017-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 33957 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15475892 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/475892
Stacked semiconductor package and method for performing bare die testing on a functional die in a stacked semiconductor package Mar 30, 2017 Issued
Array ( [id] => 12614715 [patent_doc_number] => 20180096735 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-04-05 [patent_title] => SYSTEMS, METHODS, AND APPARATUSES FOR IMPLEMENTING TESTING OF A FAR MEMORY SUBSYSTEM WITHIN TWO-LEVEL MEMORY (2LM) STACKED DIE SUBSYSTEMS [patent_app_type] => utility [patent_app_number] => 15/475902 [patent_app_country] => US [patent_app_date] => 2017-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 33952 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15475902 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/475902
Systems, methods, and apparatuses for implementing testing of a far memory subsystem within two-level memory (2LM) stacked die subsystems Mar 30, 2017 Issued
Array ( [id] => 12108858 [patent_doc_number] => 09865346 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-01-09 [patent_title] => 'Phase change memory device and method of operation' [patent_app_type] => utility [patent_app_number] => 15/475609 [patent_app_country] => US [patent_app_date] => 2017-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5491 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 223 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15475609 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/475609
Phase change memory device and method of operation Mar 30, 2017 Issued
Array ( [id] => 12026994 [patent_doc_number] => 20170317093 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-11-02 [patent_title] => 'Split-Gate, Twin-Bit Non-volatile Memory Cell' [patent_app_type] => utility [patent_app_number] => 15/476663 [patent_app_country] => US [patent_app_date] => 2017-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 27 [patent_no_of_words] => 5036 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15476663 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/476663
Split-gate, twin-bit non-volatile memory cell Mar 30, 2017 Issued
Array ( [id] => 12416985 [patent_doc_number] => 09972611 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-05-15 [patent_title] => Stacked semiconductor package having fault detection and a method for identifying a fault in a stacked package [patent_app_type] => utility [patent_app_number] => 15/475879 [patent_app_country] => US [patent_app_date] => 2017-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 31 [patent_no_of_words] => 33947 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15475879 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/475879
Stacked semiconductor package having fault detection and a method for identifying a fault in a stacked package Mar 30, 2017 Issued
Array ( [id] => 13434703 [patent_doc_number] => 20180268894 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-09-20 [patent_title] => Skewed Corner Tracking for Memory Write Operations [patent_app_type] => utility [patent_app_number] => 15/462549 [patent_app_country] => US [patent_app_date] => 2017-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2891 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15462549 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/462549
Skewed corner tracking for memory write operations Mar 16, 2017 Issued
Array ( [id] => 12195346 [patent_doc_number] => 09899081 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-02-20 [patent_title] => 'Resistive memory device and a memory system including the same' [patent_app_type] => utility [patent_app_number] => 15/450831 [patent_app_country] => US [patent_app_date] => 2017-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 19546 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15450831 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/450831
Resistive memory device and a memory system including the same Mar 5, 2017 Issued
Array ( [id] => 12026720 [patent_doc_number] => 20170316820 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-11-02 [patent_title] => 'METHOD AND APPARATUS FOR ENHANCING READ STABILITY OF A STATIC RANDOM ACCESS MEMORY CIRCUIT IN LOW VOLTAGE OPERATION' [patent_app_type] => utility [patent_app_number] => 15/447853 [patent_app_country] => US [patent_app_date] => 2017-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6160 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15447853 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/447853
Method and apparatus for enhancing read stability of a static random access memory circuit in low voltage operation Mar 1, 2017 Issued
Array ( [id] => 12235875 [patent_doc_number] => 20180068738 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-03-08 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 15/447117 [patent_app_country] => US [patent_app_date] => 2017-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 19061 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15447117 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/447117
Semiconductor memory device in which bit line pre-charging, which is based on result of verify operation, is initiated prior to completion of the verify operation Mar 1, 2017 Issued
Array ( [id] => 12249936 [patent_doc_number] => 09922717 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-03-20 [patent_title] => 'Memory device to executed read operation using read target voltage' [patent_app_type] => utility [patent_app_number] => 15/445985 [patent_app_country] => US [patent_app_date] => 2017-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 34 [patent_figures_cnt] => 41 [patent_no_of_words] => 34770 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 241 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15445985 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/445985
Memory device to executed read operation using read target voltage Feb 28, 2017 Issued
Array ( [id] => 12101913 [patent_doc_number] => 09859011 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-01-02 [patent_title] => 'Semiconductor memory device and memory system' [patent_app_type] => utility [patent_app_number] => 15/442683 [patent_app_country] => US [patent_app_date] => 2017-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 31 [patent_no_of_words] => 19813 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15442683 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/442683
Semiconductor memory device and memory system Feb 25, 2017 Issued
Array ( [id] => 11939506 [patent_doc_number] => 20170243656 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-08-24 [patent_title] => 'FLASH MEMORY DEVICE AND ERASE METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 15/435985 [patent_app_country] => US [patent_app_date] => 2017-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5390 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15435985 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/435985
Flash memory device and erase method thereof capable of reducing power consumption Feb 16, 2017 Issued
Array ( [id] => 12140941 [patent_doc_number] => 20180019024 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-01-18 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE FOR PERFORMING A POST PACKAGE REPAIR OPERATION AND OPERATING METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 15/426399 [patent_app_country] => US [patent_app_date] => 2017-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 10531 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15426399 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/426399
Semiconductor memory device for performing a post package repair operation and operating method thereof Feb 6, 2017 Issued
Array ( [id] => 12101898 [patent_doc_number] => 09858996 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-01-02 [patent_title] => 'Memory access module for performing sensing operations on storage cells of a storage device to obtain soft information and executing a program mode to control access to the storage device' [patent_app_type] => utility [patent_app_number] => 15/426070 [patent_app_country] => US [patent_app_date] => 2017-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 10326 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15426070 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/426070
Memory access module for performing sensing operations on storage cells of a storage device to obtain soft information and executing a program mode to control access to the storage device Feb 6, 2017 Issued
Array ( [id] => 12935266 [patent_doc_number] => 09830974 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-11-28 [patent_title] => SRAM with active substrate bias [patent_app_type] => utility [patent_app_number] => 15/412039 [patent_app_country] => US [patent_app_date] => 2017-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 13 [patent_no_of_words] => 5719 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15412039 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/412039
SRAM with active substrate bias Jan 21, 2017 Issued
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