Search

David Lam

Examiner (ID: 2003, Phone: (571)272-1782 , Office: P/2825 )

Most Active Art Unit
2827
Art Unit(s)
2818, 2827, 2825
Total Applications
2102
Issued Applications
2016
Pending Applications
28
Abandoned Applications
60

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 11847341 [patent_doc_number] => 09734897 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-08-15 [patent_title] => 'SRAM bitcell structures facilitating biasing of pass gate transistors' [patent_app_type] => utility [patent_app_number] => 15/397021 [patent_app_country] => US [patent_app_date] => 2017-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 30 [patent_no_of_words] => 27464 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 224 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15397021 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/397021
SRAM bitcell structures facilitating biasing of pass gate transistors Jan 2, 2017 Issued
Array ( [id] => 15414363 [patent_doc_number] => 20200027504 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-01-23 [patent_title] => SEMICONDUCTOR MEMORY DEVICES WITH BALLASTS [patent_app_type] => utility [patent_app_number] => 16/465967 [patent_app_country] => US [patent_app_date] => 2016-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12907 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16465967 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/465967
Resistive memory devices with transition metal dichalcogenide (TMD) materials as ballast resistors to control current flow through the devices Dec 29, 2016 Issued
Array ( [id] => 11571560 [patent_doc_number] => 20170110203 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-04-20 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE, METHOD OF TESTING THE SAME AND METHOD OF OPERATING THE SAME' [patent_app_type] => utility [patent_app_number] => 15/394973 [patent_app_country] => US [patent_app_date] => 2016-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 11671 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15394973 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/394973
Semiconductor memory device, method of testing the same and method of operating the same Dec 29, 2016 Issued
Array ( [id] => 12195351 [patent_doc_number] => 09899085 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-02-20 [patent_title] => 'Non-volatile FeSRAM cell capable of non-destructive read operations' [patent_app_type] => utility [patent_app_number] => 15/393585 [patent_app_country] => US [patent_app_date] => 2016-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 17 [patent_no_of_words] => 5131 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15393585 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/393585
Non-volatile FeSRAM cell capable of non-destructive read operations Dec 28, 2016 Issued
Array ( [id] => 13640303 [patent_doc_number] => 09847112 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-12-19 [patent_title] => Synchronization of data transmission with a clock signal after a memory mode switch [patent_app_type] => utility [patent_app_number] => 15/386095 [patent_app_country] => US [patent_app_date] => 2016-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 6857 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15386095 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/386095
Synchronization of data transmission with a clock signal after a memory mode switch Dec 20, 2016 Issued
Array ( [id] => 11918173 [patent_doc_number] => 09786364 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-10-10 [patent_title] => 'Low voltage selftime tracking circuitry for write assist based memory operation' [patent_app_type] => utility [patent_app_number] => 15/381501 [patent_app_country] => US [patent_app_date] => 2016-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 3494 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15381501 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/381501
Low voltage selftime tracking circuitry for write assist based memory operation Dec 15, 2016 Issued
Array ( [id] => 13667473 [patent_doc_number] => 10163916 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-12-25 [patent_title] => Compact anti-fuse memory cell using CMOS process [patent_app_type] => utility [patent_app_number] => 15/382307 [patent_app_country] => US [patent_app_date] => 2016-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 36 [patent_no_of_words] => 10060 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15382307 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/382307
Compact anti-fuse memory cell using CMOS process Dec 15, 2016 Issued
Array ( [id] => 11608369 [patent_doc_number] => 20170125672 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-05-04 [patent_title] => 'STORAGE DEVICE AND STORAGE UNIT' [patent_app_type] => utility [patent_app_number] => 15/378130 [patent_app_country] => US [patent_app_date] => 2016-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 14978 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15378130 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/378130
STORAGE DEVICE AND STORAGE UNIT Dec 13, 2016 Abandoned
Array ( [id] => 11517250 [patent_doc_number] => 20170084324 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-03-23 [patent_title] => 'MEMORY DEVICE WITH TIMING OVERLAP MODE' [patent_app_type] => utility [patent_app_number] => 15/370114 [patent_app_country] => US [patent_app_date] => 2016-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6870 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15370114 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/370114
Memory system with timing overlap mode for activate and precharge operations Dec 5, 2016 Issued
Array ( [id] => 13878239 [patent_doc_number] => 20190035460 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-01-31 [patent_title] => MEMORY CONTROLLER, MEMORY SYSTEM, AND MEMORY CONTROLLER CONTROL METHOD [patent_app_type] => utility [patent_app_number] => 16/072789 [patent_app_country] => US [patent_app_date] => 2016-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 20534 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16072789 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/072789
Memory controller and memory system for suppression of fluctuation of voltage drop Nov 30, 2016 Issued
Array ( [id] => 14332609 [patent_doc_number] => 10297329 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-05-21 [patent_title] => NAND boosting using dynamic ramping of word line voltages [patent_app_type] => utility [patent_app_number] => 15/352390 [patent_app_country] => US [patent_app_date] => 2016-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 28 [patent_no_of_words] => 14530 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15352390 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/352390
NAND boosting using dynamic ramping of word line voltages Nov 14, 2016 Issued
Array ( [id] => 11475817 [patent_doc_number] => 20170062600 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-03-02 [patent_title] => '3DIC SYSTEM WITH MEMORY' [patent_app_type] => utility [patent_app_number] => 15/351389 [patent_app_country] => US [patent_app_date] => 2016-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 134 [patent_figures_cnt] => 134 [patent_no_of_words] => 26200 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15351389 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/351389
3DIC based system with memory cells and transistors Nov 13, 2016 Issued
Array ( [id] => 12953854 [patent_doc_number] => 09837429 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-12-05 [patent_title] => Method of fabricating a three-dimensional semiconductor memory device having a plurality of memory blocks on a peripheral logic structure [patent_app_type] => utility [patent_app_number] => 15/348009 [patent_app_country] => US [patent_app_date] => 2016-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 32 [patent_no_of_words] => 12267 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15348009 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/348009
Method of fabricating a three-dimensional semiconductor memory device having a plurality of memory blocks on a peripheral logic structure Nov 9, 2016 Issued
Array ( [id] => 13667475 [patent_doc_number] => 10163917 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-12-25 [patent_title] => Cell disturb prevention using a leaker device to reduce excess charge from an electronic device [patent_app_type] => utility [patent_app_number] => 15/340682 [patent_app_country] => US [patent_app_date] => 2016-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 5539 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15340682 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/340682
Cell disturb prevention using a leaker device to reduce excess charge from an electronic device Oct 31, 2016 Issued
Array ( [id] => 13187667 [patent_doc_number] => 10109359 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-10-23 [patent_title] => Nonvolatile semiconductor memory including a read operation [patent_app_type] => utility [patent_app_number] => 15/337592 [patent_app_country] => US [patent_app_date] => 2016-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 22 [patent_no_of_words] => 11767 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15337592 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/337592
Nonvolatile semiconductor memory including a read operation Oct 27, 2016 Issued
Array ( [id] => 12257022 [patent_doc_number] => 09929173 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-03-27 [patent_title] => 'Method of controlling a semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 15/331026 [patent_app_country] => US [patent_app_date] => 2016-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 15 [patent_no_of_words] => 4690 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15331026 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/331026
Method of controlling a semiconductor memory device Oct 20, 2016 Issued
Array ( [id] => 11665112 [patent_doc_number] => 20170153831 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-01 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE WITH OPERATION ENVIRONMENT INFORMATION STORING CIRCUIT AND COMMAND STORING FUNCTION' [patent_app_type] => utility [patent_app_number] => 15/278078 [patent_app_country] => US [patent_app_date] => 2016-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 10017 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15278078 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/278078
Semiconductor memory device with operation environment information storing circuit and command storing function Sep 27, 2016 Issued
Array ( [id] => 12019473 [patent_doc_number] => 09812182 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-11-07 [patent_title] => 'Memory devices with improved refreshing operation' [patent_app_type] => utility [patent_app_number] => 15/250212 [patent_app_country] => US [patent_app_date] => 2016-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 4254 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15250212 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/250212
Memory devices with improved refreshing operation Aug 28, 2016 Issued
Array ( [id] => 11339387 [patent_doc_number] => 20160365143 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-12-15 [patent_title] => 'SEMICONDUCTOR STORAGE DEVICE WITH VOLTAGE GENERATOR' [patent_app_type] => utility [patent_app_number] => 15/248216 [patent_app_country] => US [patent_app_date] => 2016-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 11973 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15248216 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/248216
Semiconductor storage device with voltage generator which generates voltages and currents for read and write operations Aug 25, 2016 Issued
Array ( [id] => 11571550 [patent_doc_number] => 20170110194 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-04-20 [patent_title] => 'Power Driven Optimization For Flash Memory' [patent_app_type] => utility [patent_app_number] => 15/244947 [patent_app_country] => US [patent_app_date] => 2016-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3577 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15244947 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/244947
Power Driven Optimization For Flash Memory Aug 22, 2016 Abandoned
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