Search

David Lam

Examiner (ID: 9276, Phone: (571)272-1782 , Office: P/2825 )

Most Active Art Unit
2827
Art Unit(s)
2818, 2825, 2827
Total Applications
2102
Issued Applications
2016
Pending Applications
28
Abandoned Applications
60

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 11861720 [patent_doc_number] => 09741408 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-08-22 [patent_title] => 'Semiconductor memory device having dummy word lines and operating method thereof' [patent_app_type] => utility [patent_app_number] => 14/924523 [patent_app_country] => US [patent_app_date] => 2015-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 5155 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14924523 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/924523
Semiconductor memory device having dummy word lines and operating method thereof Oct 26, 2015 Issued
Array ( [id] => 10809334 [patent_doc_number] => 20160155492 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-06-02 [patent_title] => 'NOVEL FINFET 6T SRAM CELL STRUCTURE' [patent_app_type] => utility [patent_app_number] => 14/921963 [patent_app_country] => US [patent_app_date] => 2015-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 11633 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14921963 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/921963
FinFET 6T SRAM cell structure Oct 22, 2015 Issued
Array ( [id] => 14606735 [patent_doc_number] => 10356573 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-07-16 [patent_title] => Thermostat synchronization via remote input device [patent_app_type] => utility [patent_app_number] => 14/920188 [patent_app_country] => US [patent_app_date] => 2015-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 22 [patent_no_of_words] => 3974 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14920188 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/920188
Thermostat synchronization via remote input device Oct 21, 2015 Issued
Array ( [id] => 11411485 [patent_doc_number] => 09558794 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-01-31 [patent_title] => 'Semiconductor memory device including peripheral circuit for performing program and read opeartions and operating method thereof' [patent_app_type] => utility [patent_app_number] => 14/918327 [patent_app_country] => US [patent_app_date] => 2015-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 5907 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14918327 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/918327
Semiconductor memory device including peripheral circuit for performing program and read opeartions and operating method thereof Oct 19, 2015 Issued
Array ( [id] => 10696654 [patent_doc_number] => 20160042801 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-02-11 [patent_title] => 'NONVOLATILE SEMICONDUCTOR MEMORY' [patent_app_type] => utility [patent_app_number] => 14/886193 [patent_app_country] => US [patent_app_date] => 2015-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 12227 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14886193 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/886193
Nonvolatile semiconductor memory and verify read operation Oct 18, 2015 Issued
Array ( [id] => 10689253 [patent_doc_number] => 20160035398 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-02-04 [patent_title] => 'MEMORY DEVICES' [patent_app_type] => utility [patent_app_number] => 14/881492 [patent_app_country] => US [patent_app_date] => 2015-10-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4219 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14881492 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/881492
Memory devices with improved refreshing operation Oct 12, 2015 Issued
Array ( [id] => 10772243 [patent_doc_number] => 20160118399 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-04-28 [patent_title] => 'THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 14/878453 [patent_app_country] => US [patent_app_date] => 2015-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 30 [patent_no_of_words] => 12489 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14878453 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/878453
Three-dimensional semiconductor memory device Oct 7, 2015 Issued
Array ( [id] => 12416346 [patent_doc_number] => 09972395 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-05-15 [patent_title] => Row and column decoders comprising fully depleted silicon-on-insulator transistors for use in flash memory systems [patent_app_type] => utility [patent_app_number] => 14/875533 [patent_app_country] => US [patent_app_date] => 2015-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 4757 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14875533 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/875533
Row and column decoders comprising fully depleted silicon-on-insulator transistors for use in flash memory systems Oct 4, 2015 Issued
Array ( [id] => 12435756 [patent_doc_number] => 09978434 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-05-22 [patent_title] => Method for writing in a magnetic device having a plurality of magnetic logical unit cells using a single programming current [patent_app_type] => utility [patent_app_number] => 15/516085 [patent_app_country] => US [patent_app_date] => 2015-10-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 6610 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 210 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15516085 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/516085
Method for writing in a magnetic device having a plurality of magnetic logical unit cells using a single programming current Oct 1, 2015 Issued
Array ( [id] => 10758370 [patent_doc_number] => 20160104521 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-04-14 [patent_title] => 'SEMICONDUCTOR DEVICE, CIRCUIT BOARD, AND ELECTRONIC DEVICE' [patent_app_type] => utility [patent_app_number] => 14/872535 [patent_app_country] => US [patent_app_date] => 2015-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 27 [patent_no_of_words] => 27529 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14872535 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/872535
Semiconductor device with stacked structure of memory cells over sensing amplifiers, circuit board, and electronic device Sep 30, 2015 Issued
Array ( [id] => 10673811 [patent_doc_number] => 20160019956 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-01-21 [patent_title] => 'ELECTRONIC DEVICE' [patent_app_type] => utility [patent_app_number] => 14/867894 [patent_app_country] => US [patent_app_date] => 2015-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 28 [patent_no_of_words] => 20201 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14867894 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/867894
Electric device having wire contacts coupled to stack structures with variable resistance elements Sep 27, 2015 Issued
Array ( [id] => 10747243 [patent_doc_number] => 20160093394 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-03-31 [patent_title] => 'STORAGE DEVICE AND OPERATING METHOD OF STORAGE DEVICE' [patent_app_type] => utility [patent_app_number] => 14/856695 [patent_app_country] => US [patent_app_date] => 2015-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 17324 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14856695 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/856695
Storage device and operating method of storage device Sep 16, 2015 Issued
Array ( [id] => 11861722 [patent_doc_number] => 09741410 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-08-22 [patent_title] => 'Memory circuitry using write assist voltage boost' [patent_app_type] => utility [patent_app_number] => 14/857527 [patent_app_country] => US [patent_app_date] => 2015-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3220 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14857527 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/857527
Memory circuitry using write assist voltage boost Sep 16, 2015 Issued
Array ( [id] => 11207630 [patent_doc_number] => 09437259 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-09-06 [patent_title] => 'Memory system including memory chips having serially and parallel arranging input/output' [patent_app_type] => utility [patent_app_number] => 14/857511 [patent_app_country] => US [patent_app_date] => 2015-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8866 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 263 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14857511 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/857511
Memory system including memory chips having serially and parallel arranging input/output Sep 16, 2015 Issued
Array ( [id] => 11644890 [patent_doc_number] => 09666278 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-05-30 [patent_title] => 'Content addressable memory array comprising geometric footprint and RAM cell block located between two parts of a CAM cell block' [patent_app_type] => utility [patent_app_number] => 14/855615 [patent_app_country] => US [patent_app_date] => 2015-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 6465 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14855615 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/855615
Content addressable memory array comprising geometric footprint and RAM cell block located between two parts of a CAM cell block Sep 15, 2015 Issued
Array ( [id] => 11103657 [patent_doc_number] => 20160300627 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-10-13 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 14/855071 [patent_app_country] => US [patent_app_date] => 2015-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 12994 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14855071 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/855071
Semiconductor memory device including controller and fuse circuits for performing repair operation Sep 14, 2015 Issued
Array ( [id] => 11796544 [patent_doc_number] => 09406387 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-08-02 [patent_title] => 'Charge redistribution during erase in charge trapping memory' [patent_app_type] => utility [patent_app_number] => 14/851639 [patent_app_country] => US [patent_app_date] => 2015-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 33 [patent_no_of_words] => 13502 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14851639 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/851639
Charge redistribution during erase in charge trapping memory Sep 10, 2015 Issued
Array ( [id] => 11502627 [patent_doc_number] => 20170076812 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-03-16 [patent_title] => 'Verify Operations Using Different Sense Node Voltages In A Memory Device' [patent_app_type] => utility [patent_app_number] => 14/849879 [patent_app_country] => US [patent_app_date] => 2015-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 18851 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14849879 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/849879
Memory device which performs verify operations using different sense node pre-charge voltages and a common discharge period Sep 9, 2015 Issued
Array ( [id] => 11050622 [patent_doc_number] => 20160247581 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-08-25 [patent_title] => 'MEMORY SYSTEM, MEMORY CONTROLLER AND MEMORY CONTROL METHOD' [patent_app_type] => utility [patent_app_number] => 14/849145 [patent_app_country] => US [patent_app_date] => 2015-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 8921 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14849145 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/849145
MEMORY SYSTEM, MEMORY CONTROLLER AND MEMORY CONTROL METHOD Sep 8, 2015 Abandoned
Array ( [id] => 11411513 [patent_doc_number] => 09558823 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-01-31 [patent_title] => 'Resistance drift recovery method for MLC PCM' [patent_app_type] => utility [patent_app_number] => 14/846393 [patent_app_country] => US [patent_app_date] => 2015-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 29 [patent_no_of_words] => 8900 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14846393 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/846393
Resistance drift recovery method for MLC PCM Sep 3, 2015 Issued
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