David Lam

Array ( [id] => 10551118 [patent_doc_number] => 09275749 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-03-01 [patent_title] => 'Internal power voltage generating circuit, semiconductor memory device and semiconductor device' [patent_app_type] => utility [patent_app_number] => 14/718101 [patent_app_country] => US [patent_app_date] => 2015-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 6997 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 238 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14718101 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10551081 [patent_doc_number] => 09275712 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-03-01 [patent_title] => 'Semiconductor device and semiconductor system' [patent_app_type] => utility [patent_app_number] => 14/717513 [patent_app_country] => US [patent_app_date] => 2015-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4803 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14717513 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10673816 [patent_doc_number] => 20160019961 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-01-21 [patent_title] => 'CONTROLLING ADJUSTABLE RESISTANCE BIT LINES CONNECTED TO WORD LINE COMBS' [patent_app_type] => utility [patent_app_number] => 14/715583 [patent_app_country] => US [patent_app_date] => 2015-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 63 [patent_figures_cnt] => 63 [patent_no_of_words] => 37954 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14715583 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11787681 [patent_doc_number] => 09397145 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-07-19 [patent_title] => 'Memory structures and related cross-point memory arrays, electronic systems, and methods of forming memory structures' [patent_app_type] => utility [patent_app_number] => 14/712241 [patent_app_country] => US [patent_app_date] => 2015-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 10761 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14712241 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10350691 [patent_doc_number] => 20150235696 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-08-20 [patent_title] => 'MEMORY CELL WITH IMPROVED WRITE MARGIN' [patent_app_type] => utility [patent_app_number] => 14/703723 [patent_app_country] => US [patent_app_date] => 2015-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 9580 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14703723 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11839838 [patent_doc_number] => 20170221558 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-08-03 [patent_title] => 'MEMRISTOR APPARATUS WITH VARIABLE TRANSMISSION DELAY' [patent_app_type] => utility [patent_app_number] => 15/500555 [patent_app_country] => US [patent_app_date] => 2015-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 7782 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15500555 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10794854 [patent_doc_number] => 20160141011 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-05-19 [patent_title] => 'SEMICONDUCTOR DEVICE AND OPERATING METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 14/692123 [patent_app_country] => US [patent_app_date] => 2015-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5938 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14692123 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10336372 [patent_doc_number] => 20150221377 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-08-06 [patent_title] => 'BUFFERING SYSTEMS FOR ACCESSING MULTIPLE LAYERS OF MEMORY IN INTEGRATED CIRCUITS' [patent_app_type] => utility [patent_app_number] => 14/685342 [patent_app_country] => US [patent_app_date] => 2015-04-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 8022 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14685342 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10479161 [patent_doc_number] => 20150364178 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-12-17 [patent_title] => 'MEMORY CORES OF RESISTIVE TYPE MEMORY DEVICES, RESISTIVE TYPE MEMORY DEVICES AND METHOD OF SENSING DATA IN THE SAME' [patent_app_type] => utility [patent_app_number] => 14/677991 [patent_app_country] => US [patent_app_date] => 2015-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 28 [patent_no_of_words] => 17744 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14677991 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14267203 [patent_doc_number] => 10283171 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-05-07 [patent_title] => Stacked die semiconductor device with separate bit line and bit line bar interconnect structures [patent_app_type] => utility [patent_app_number] => 14/673108 [patent_app_country] => US [patent_app_date] => 2015-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4931 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14673108 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10309205 [patent_doc_number] => 20150194206 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-07-09 [patent_title] => 'METHOD OF WRITING TO AND READING DATA FROM A THREE-DIMENSIONAL TWO PORT REGISTER FILE' [patent_app_type] => utility [patent_app_number] => 14/666373 [patent_app_country] => US [patent_app_date] => 2015-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6826 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14666373 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11194118 [patent_doc_number] => 09424936 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-08-23 [patent_title] => 'Current leakage reduction in 3D NAND memory' [patent_app_type] => utility [patent_app_number] => 14/666147 [patent_app_country] => US [patent_app_date] => 2015-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7700 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14666147 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10370156 [patent_doc_number] => 20150255161 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-09-10 [patent_title] => 'NONVOLATILE MEMORY SYSTEM AND METHOD OF OPERATING THE SAME' [patent_app_type] => utility [patent_app_number] => 14/636577 [patent_app_country] => US [patent_app_date] => 2015-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 11798 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14636577 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14393485 [patent_doc_number] => 10310019 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-06-04 [patent_title] => System for estimating the state of health of a battery using liquid-phase diffusivity of lithium-ion parameters [patent_app_type] => utility [patent_app_number] => 14/636847 [patent_app_country] => US [patent_app_date] => 2015-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3639 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14636847 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10502274 [patent_doc_number] => 09230676 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-01-05 [patent_title] => 'Weak erase of a dummy memory cell to counteract inadvertent programming' [patent_app_type] => utility [patent_app_number] => 14/612561 [patent_app_country] => US [patent_app_date] => 2015-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 51 [patent_no_of_words] => 19423 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 227 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14612561 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10530394 [patent_doc_number] => 09256530 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-02-09 [patent_title] => 'Nonvolatile memory device and sub-block managing method thereof' [patent_app_type] => utility [patent_app_number] => 14/610512 [patent_app_country] => US [patent_app_date] => 2015-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 12258 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14610512 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11510522 [patent_doc_number] => 09601692 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-03-21 [patent_title] => 'Hetero-switching layer in a RRAM device and method' [patent_app_type] => utility [patent_app_number] => 14/611022 [patent_app_country] => US [patent_app_date] => 2015-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 22 [patent_no_of_words] => 10193 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 218 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14611022 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10112415 [patent_doc_number] => 09147837 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2015-09-29 [patent_title] => 'Resistive memory cell and method for forming a resistive memory cell' [patent_app_type] => utility [patent_app_number] => 14/609853 [patent_app_country] => US [patent_app_date] => 2015-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 27 [patent_no_of_words] => 4639 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14609853 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11760088 [patent_doc_number] => 20170206957 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-07-20 [patent_title] => 'SENSING AN OUTPUT SIGNAL IN A CROSSBAR ARRAY' [patent_app_type] => utility [patent_app_number] => 15/329207 [patent_app_country] => US [patent_app_date] => 2015-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 9611 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15329207 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10239553 [patent_doc_number] => 20150124548 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-05-07 [patent_title] => 'SWITCHING CIRCUIT' [patent_app_type] => utility [patent_app_number] => 14/597897 [patent_app_country] => US [patent_app_date] => 2015-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 10229 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14597897 [rel_patent_id] =>[rel_patent_doc_number] =>)