Search

David Lam

Examiner (ID: 9276, Phone: (571)272-1782 , Office: P/2825 )

Most Active Art Unit
2827
Art Unit(s)
2818, 2825, 2827
Total Applications
2102
Issued Applications
2016
Pending Applications
28
Abandoned Applications
60

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 10502231 [patent_doc_number] => 09230633 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-01-05 [patent_title] => 'Memory device with timing overlap mode' [patent_app_type] => utility [patent_app_number] => 14/595568 [patent_app_country] => US [patent_app_date] => 2015-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6907 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14595568 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/595568
Memory device with timing overlap mode Jan 12, 2015 Issued
Array ( [id] => 11791574 [patent_doc_number] => 09401214 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-07-26 [patent_title] => 'Three-dimensional memory device and operating method of a storage device including the same' [patent_app_type] => utility [patent_app_number] => 14/592459 [patent_app_country] => US [patent_app_date] => 2015-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 27 [patent_no_of_words] => 9983 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14592459 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/592459
Three-dimensional memory device and operating method of a storage device including the same Jan 7, 2015 Issued
Array ( [id] => 11796837 [patent_doc_number] => 09406685 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-08-02 [patent_title] => 'Flash memory unit and memory array, and programming, erasing and reading method thereof' [patent_app_type] => utility [patent_app_number] => 14/583927 [patent_app_country] => US [patent_app_date] => 2014-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 4593 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 322 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14583927 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/583927
Flash memory unit and memory array, and programming, erasing and reading method thereof Dec 28, 2014 Issued
Array ( [id] => 11539290 [patent_doc_number] => 09613704 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-04-04 [patent_title] => '2D/3D NAND memory array with bit-line hierarchical structure for multi-page concurrent SLC/MLC program and program-verify' [patent_app_type] => utility [patent_app_number] => 14/583178 [patent_app_country] => US [patent_app_date] => 2014-12-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 42 [patent_figures_cnt] => 42 [patent_no_of_words] => 75453 [patent_no_of_claims] => 124 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 590 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14583178 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/583178
2D/3D NAND memory array with bit-line hierarchical structure for multi-page concurrent SLC/MLC program and program-verify Dec 24, 2014 Issued
Array ( [id] => 11775848 [patent_doc_number] => 09384792 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-07-05 [patent_title] => 'Offset-cancelling self-reference STT-MRAM sense amplifier' [patent_app_type] => utility [patent_app_number] => 14/580589 [patent_app_country] => US [patent_app_date] => 2014-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4356 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 311 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14580589 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/580589
Offset-cancelling self-reference STT-MRAM sense amplifier Dec 22, 2014 Issued
Array ( [id] => 10984014 [patent_doc_number] => 20160180958 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-06-23 [patent_title] => 'DYNAMICALLY COMPENSATING FOR DEGRADATION OF A NON-VOLATILE MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 14/579971 [patent_app_country] => US [patent_app_date] => 2014-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6683 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14579971 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/579971
Dynamically compensating for degradation of a non-volatile memory device Dec 21, 2014 Issued
Array ( [id] => 10645127 [patent_doc_number] => 09362000 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-06-07 [patent_title] => 'Memory system and management method thereof' [patent_app_type] => utility [patent_app_number] => 14/579127 [patent_app_country] => US [patent_app_date] => 2014-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 4716 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14579127 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/579127
Memory system and management method thereof Dec 21, 2014 Issued
Array ( [id] => 10512658 [patent_doc_number] => 09240236 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-01-19 [patent_title] => 'Switching conditions for resistive random access memory cells' [patent_app_type] => utility [patent_app_number] => 14/577613 [patent_app_country] => US [patent_app_date] => 2014-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 10213 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 279 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14577613 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/577613
Switching conditions for resistive random access memory cells Dec 18, 2014 Issued
Array ( [id] => 10479192 [patent_doc_number] => 20150364208 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-12-17 [patent_title] => 'SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 14/572071 [patent_app_country] => US [patent_app_date] => 2014-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 8372 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14572071 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/572071
Semiconductor device with pass/fail circuit Dec 15, 2014 Issued
Array ( [id] => 10570048 [patent_doc_number] => 09293224 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-03-22 [patent_title] => 'Double data rate in parallel testing' [patent_app_type] => utility [patent_app_number] => 14/569983 [patent_app_country] => US [patent_app_date] => 2014-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2627 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14569983 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/569983
Double data rate in parallel testing Dec 14, 2014 Issued
Array ( [id] => 10200584 [patent_doc_number] => 20150085570 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-03-26 [patent_title] => 'PHASE CHANGE MEMORY MASK' [patent_app_type] => utility [patent_app_number] => 14/560410 [patent_app_country] => US [patent_app_date] => 2014-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6843 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14560410 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/560410
Phase change memory with mask receiver Dec 3, 2014 Issued
Array ( [id] => 10269093 [patent_doc_number] => 20150154089 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-06-04 [patent_title] => 'ERROR RECOVERY FOR FLASH MEMORY' [patent_app_type] => utility [patent_app_number] => 14/558486 [patent_app_country] => US [patent_app_date] => 2014-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 6965 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14558486 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/558486
Error recovery for flash memory Dec 1, 2014 Issued
Array ( [id] => 11483096 [patent_doc_number] => 09589646 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-03-07 [patent_title] => 'Page buffer circuit having bias voltage application unit and operating method of same' [patent_app_type] => utility [patent_app_number] => 14/554293 [patent_app_country] => US [patent_app_date] => 2014-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 34 [patent_figures_cnt] => 35 [patent_no_of_words] => 13850 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14554293 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/554293
Page buffer circuit having bias voltage application unit and operating method of same Nov 25, 2014 Issued
Array ( [id] => 10200596 [patent_doc_number] => 20150085582 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-03-26 [patent_title] => 'PROGRAMMING METHOD OF NONVOLATILE MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 14/555172 [patent_app_country] => US [patent_app_date] => 2014-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6392 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14555172 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/555172
Programming method of nonvolatile memory device Nov 25, 2014 Issued
Array ( [id] => 11775900 [patent_doc_number] => 09384845 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-07-05 [patent_title] => 'Partial erase of nonvolatile memory blocks' [patent_app_type] => utility [patent_app_number] => 14/546133 [patent_app_country] => US [patent_app_date] => 2014-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 26 [patent_no_of_words] => 9780 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14546133 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/546133
Partial erase of nonvolatile memory blocks Nov 17, 2014 Issued
Array ( [id] => 10537474 [patent_doc_number] => 09263107 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-02-16 [patent_title] => 'Load isolation for pad signal monitoring' [patent_app_type] => utility [patent_app_number] => 14/535271 [patent_app_country] => US [patent_app_date] => 2014-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5110 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14535271 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/535271
Load isolation for pad signal monitoring Nov 5, 2014 Issued
Array ( [id] => 11080239 [patent_doc_number] => 20160277203 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-09-22 [patent_title] => 'SMART HOME SCENE SWITCHING METHOD AND SYSTEM' [patent_app_type] => utility [patent_app_number] => 15/035913 [patent_app_country] => US [patent_app_date] => 2014-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5995 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15035913 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/035913
Smart home scene switching method and system Oct 28, 2014 Issued
Array ( [id] => 10190050 [patent_doc_number] => 09219482 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-12-22 [patent_title] => 'High voltage switch circuit and nonvolatile memory including the same' [patent_app_type] => utility [patent_app_number] => 14/523461 [patent_app_country] => US [patent_app_date] => 2014-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 3727 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14523461 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/523461
High voltage switch circuit and nonvolatile memory including the same Oct 23, 2014 Issued
Array ( [id] => 10603823 [patent_doc_number] => 09324392 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-04-26 [patent_title] => 'Memory device and method of performing a write operation in a memory device' [patent_app_type] => utility [patent_app_number] => 14/521635 [patent_app_country] => US [patent_app_date] => 2014-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 8738 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14521635 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/521635
Memory device and method of performing a write operation in a memory device Oct 22, 2014 Issued
Array ( [id] => 9898891 [patent_doc_number] => 20150054090 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-02-26 [patent_title] => '3DIC SYSTEM WITH A TWO STABLE STATE MEMORY' [patent_app_type] => utility [patent_app_number] => 14/506160 [patent_app_country] => US [patent_app_date] => 2014-10-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 134 [patent_figures_cnt] => 134 [patent_no_of_words] => 26103 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14506160 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/506160
3DIC system with a two stable state memory and back-bias region Oct 2, 2014 Issued
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