
David Lam
Examiner (ID: 9276, Phone: (571)272-1782 , Office: P/2825 )
| Most Active Art Unit | 2827 |
| Art Unit(s) | 2818, 2825, 2827 |
| Total Applications | 2102 |
| Issued Applications | 2016 |
| Pending Applications | 28 |
| Abandoned Applications | 60 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 10651924
[patent_doc_number] => 09368184
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2016-06-14
[patent_title] => 'Memory refresh methods, memory section control circuits, and apparatuses'
[patent_app_type] => utility
[patent_app_number] => 14/505717
[patent_app_country] => US
[patent_app_date] => 2014-10-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 4863
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 48
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14505717
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/505717 | Memory refresh methods, memory section control circuits, and apparatuses | Oct 2, 2014 | Issued |
Array
(
[id] => 11079868
[patent_doc_number] => 20160276832
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-09-22
[patent_title] => 'ENERGY MANAGEMENT SYSTEM FOR ADJUSTING ENERGY SUPPLY AND DEMAND OF PLURALITY OF DISTRICTS, AND ENERGY MANAGEMENT METHOD'
[patent_app_type] => utility
[patent_app_number] => 15/028183
[patent_app_country] => US
[patent_app_date] => 2014-10-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 16
[patent_no_of_words] => 13443
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15028183
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/028183 | ENERGY MANAGEMENT SYSTEM FOR ADJUSTING ENERGY SUPPLY AND DEMAND OF PLURALITY OF DISTRICTS, AND ENERGY MANAGEMENT METHOD | Oct 2, 2014 | Abandoned |
Array
(
[id] => 10195553
[patent_doc_number] => 09224466
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2015-12-29
[patent_title] => 'Dual capacitor sense amplifier and methods therefor'
[patent_app_type] => utility
[patent_app_number] => 14/499717
[patent_app_country] => US
[patent_app_date] => 2014-09-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 20
[patent_figures_cnt] => 22
[patent_no_of_words] => 12910
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 164
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14499717
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/499717 | Dual capacitor sense amplifier and methods therefor | Sep 28, 2014 | Issued |
Array
(
[id] => 10747211
[patent_doc_number] => 20160093363
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-03-31
[patent_title] => 'MULTI-PORT MEMORY CIRCUITS'
[patent_app_type] => utility
[patent_app_number] => 14/499041
[patent_app_country] => US
[patent_app_date] => 2014-09-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 3226
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14499041
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/499041 | Multi-port memory circuits | Sep 25, 2014 | Issued |
Array
(
[id] => 10583488
[patent_doc_number] => 09305612
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2016-04-05
[patent_title] => 'Programmable LSI with multiple transistors in a memory element'
[patent_app_type] => utility
[patent_app_number] => 14/493737
[patent_app_country] => US
[patent_app_date] => 2014-09-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 19
[patent_figures_cnt] => 47
[patent_no_of_words] => 32567
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 79
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14493737
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/493737 | Programmable LSI with multiple transistors in a memory element | Sep 22, 2014 | Issued |
Array
(
[id] => 10440263
[patent_doc_number] => 20150325275
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-11-12
[patent_title] => 'MEMORY GENERATING METHOD OF MEMORY COMPILER AND GENERATED MEMORY'
[patent_app_type] => utility
[patent_app_number] => 14/492687
[patent_app_country] => US
[patent_app_date] => 2014-09-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 3645
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14492687
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/492687 | Memory generating method of memory compiler and generated memory | Sep 21, 2014 | Issued |
Array
(
[id] => 11764970
[patent_doc_number] => 09373410
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2016-06-21
[patent_title] => 'MLC OTP operation in A-Si RRAM'
[patent_app_type] => utility
[patent_app_number] => 14/479111
[patent_app_country] => US
[patent_app_date] => 2014-09-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 13
[patent_no_of_words] => 12646
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 135
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14479111
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/479111 | MLC OTP operation in A-Si RRAM | Sep 4, 2014 | Issued |
Array
(
[id] => 10966076
[patent_doc_number] => 20140369108
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-12-18
[patent_title] => 'SYSTEM AND A METHOD FOR DESIGNING A HYBRID MEMORY CELL WITH MEMRISTOR AND COMPLEMENTARY METAL-OXIDE SEMICONDUCTOR'
[patent_app_type] => utility
[patent_app_number] => 14/474339
[patent_app_country] => US
[patent_app_date] => 2014-09-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 7595
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14474339
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/474339 | System and a method for designing a hybrid memory cell with memristor and complementary metal-oxide semiconductor | Sep 1, 2014 | Issued |
Array
(
[id] => 10717940
[patent_doc_number] => 20160064087
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-03-03
[patent_title] => 'Charge Redistribution During Erase In Charge Trapping Memory'
[patent_app_type] => utility
[patent_app_number] => 14/472889
[patent_app_country] => US
[patent_app_date] => 2014-08-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 16
[patent_no_of_words] => 13437
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14472889
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/472889 | Charge redistribution during erase in charge trapping memory | Aug 28, 2014 | Issued |
Array
(
[id] => 10285741
[patent_doc_number] => 20150170739
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-06-18
[patent_title] => 'NONVOLATILE MEMORY CELLS PROGRAMABLE BY PHASE CHANGE AND METHOD'
[patent_app_type] => utility
[patent_app_number] => 14/469995
[patent_app_country] => US
[patent_app_date] => 2014-08-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 14
[patent_no_of_words] => 8239
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14469995
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/469995 | Nonvolatile memory cells programable by phase change and method | Aug 26, 2014 | Issued |
Array
(
[id] => 10709756
[patent_doc_number] => 20160055903
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-02-25
[patent_title] => 'PSEUDO DUAL PORT MEMORY'
[patent_app_type] => utility
[patent_app_number] => 14/464627
[patent_app_country] => US
[patent_app_date] => 2014-08-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 6431
[patent_no_of_claims] => 27
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14464627
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/464627 | Pseudo dual port memory with dual latch flip-flop | Aug 19, 2014 | Issued |
Array
(
[id] => 10092869
[patent_doc_number] => 09129697
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2015-09-08
[patent_title] => 'Method of providing an operating voltage in a memory device and a memory controller for the memory device'
[patent_app_type] => utility
[patent_app_number] => 14/458453
[patent_app_country] => US
[patent_app_date] => 2014-08-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 14
[patent_no_of_words] => 5857
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 208
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14458453
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/458453 | Method of providing an operating voltage in a memory device and a memory controller for the memory device | Aug 12, 2014 | Issued |
Array
(
[id] => 10537494
[patent_doc_number] => 09263127
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2016-02-16
[patent_title] => 'Memory with specific driving mechanism applied on source line'
[patent_app_type] => utility
[patent_app_number] => 14/458037
[patent_app_country] => US
[patent_app_date] => 2014-08-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 10
[patent_no_of_words] => 3390
[patent_no_of_claims] => 28
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 163
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14458037
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/458037 | Memory with specific driving mechanism applied on source line | Aug 11, 2014 | Issued |
Array
(
[id] => 10943628
[patent_doc_number] => 20140346649
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-11-27
[patent_title] => 'Three dimension structure memory'
[patent_app_type] => utility
[patent_app_number] => 14/457515
[patent_app_country] => US
[patent_app_date] => 2014-08-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 7178
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14457515
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/457515 | Three dimension structure memory | Aug 11, 2014 | Issued |
Array
(
[id] => 10189447
[patent_doc_number] => 09218874
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2015-12-22
[patent_title] => 'Multi-pulse programming cycle of non-volatile memory for enhanced de-trapping'
[patent_app_type] => utility
[patent_app_number] => 14/456853
[patent_app_country] => US
[patent_app_date] => 2014-08-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 22
[patent_no_of_words] => 8335
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 284
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14456853
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/456853 | Multi-pulse programming cycle of non-volatile memory for enhanced de-trapping | Aug 10, 2014 | Issued |
Array
(
[id] => 10689281
[patent_doc_number] => 20160035426
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-02-04
[patent_title] => 'Bias To Detect And Prevent Short Circuits In Three-Dimensional Memory Device'
[patent_app_type] => utility
[patent_app_number] => 14/451223
[patent_app_country] => US
[patent_app_date] => 2014-08-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 23
[patent_figures_cnt] => 23
[patent_no_of_words] => 14418
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14451223
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/451223 | Bias to detect and prevent short circuits in three-dimensional memory device | Aug 3, 2014 | Issued |
Array
(
[id] => 10603851
[patent_doc_number] => 09324420
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2016-04-26
[patent_title] => 'Method of estimating deterioration state of memory device and related method of wear leveling'
[patent_app_type] => utility
[patent_app_number] => 14/446347
[patent_app_country] => US
[patent_app_date] => 2014-07-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
[patent_figures_cnt] => 28
[patent_no_of_words] => 10955
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 155
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14446347
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/446347 | Method of estimating deterioration state of memory device and related method of wear leveling | Jul 29, 2014 | Issued |
Array
(
[id] => 9929879
[patent_doc_number] => 20150078070
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-03-19
[patent_title] => 'MAGNETIC MEMORY DEVICE AND DRIVING METHOD FOR THE SAME'
[patent_app_type] => utility
[patent_app_number] => 14/445331
[patent_app_country] => US
[patent_app_date] => 2014-07-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 31
[patent_figures_cnt] => 31
[patent_no_of_words] => 16763
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14445331
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/445331 | Magnetic memory device and driving method for the same | Jul 28, 2014 | Issued |
Array
(
[id] => 10544673
[patent_doc_number] => 09269810
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2016-02-23
[patent_title] => 'Semiconductor device having wave gate'
[patent_app_type] => utility
[patent_app_number] => 14/444155
[patent_app_country] => US
[patent_app_date] => 2014-07-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 22
[patent_no_of_words] => 7882
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 212
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14444155
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/444155 | Semiconductor device having wave gate | Jul 27, 2014 | Issued |
Array
(
[id] => 10681384
[patent_doc_number] => 20160027529
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-01-28
[patent_title] => 'Address Fault Detection Circuit'
[patent_app_type] => utility
[patent_app_number] => 14/339049
[patent_app_country] => US
[patent_app_date] => 2014-07-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 16659
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14339049
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/339049 | Address fault detection circuit | Jul 22, 2014 | Issued |