Search

David Lam

Examiner (ID: 9276, Phone: (571)272-1782 , Office: P/2825 )

Most Active Art Unit
2827
Art Unit(s)
2818, 2825, 2827
Total Applications
2102
Issued Applications
2016
Pending Applications
28
Abandoned Applications
60

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 10923921 [patent_doc_number] => 20140326942 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-11-06 [patent_title] => 'NON-VOLATILE MEMORY DEVICE HAVING MULTI-LEVEL CELLS AND METHOD OF FORMING THE SAME' [patent_app_type] => utility [patent_app_number] => 14/336007 [patent_app_country] => US [patent_app_date] => 2014-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 12556 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14336007 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/336007
Non-volatile memory device having multi-level cells and method of forming the same Jul 20, 2014 Issued
Array ( [id] => 10092874 [patent_doc_number] => 09129702 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-09-08 [patent_title] => 'Method of refreshing volatile memory device' [patent_app_type] => utility [patent_app_number] => 14/336337 [patent_app_country] => US [patent_app_date] => 2014-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 19 [patent_no_of_words] => 12956 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14336337 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/336337
Method of refreshing volatile memory device Jul 20, 2014 Issued
Array ( [id] => 10918184 [patent_doc_number] => 20140321203 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-10-30 [patent_title] => 'METHOD FOR PERFORMING MEMORY ACCESS MANAGEMENT, AND ASSOCIATED MEMORY DEVICE AND CONTROLLER THEREOF' [patent_app_type] => utility [patent_app_number] => 14/327580 [patent_app_country] => US [patent_app_date] => 2014-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 10604 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14327580 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/327580
Method for performing memory access management, and associated memory device and controller thereof Jul 9, 2014 Issued
Array ( [id] => 10073226 [patent_doc_number] => 09111587 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-08-18 [patent_title] => 'Stacked memory with redundancy' [patent_app_type] => utility [patent_app_number] => 14/319544 [patent_app_country] => US [patent_app_date] => 2014-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6498 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14319544 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/319544
Stacked memory with redundancy Jun 29, 2014 Issued
Array ( [id] => 10803253 [patent_doc_number] => 20160149410 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-05-26 [patent_title] => 'DEVICE FOR CONTROLLING A POWER LOAD IN AN ELECTRICAL NETWORK, AND ASSOCIATED METHOD AND SYSTEM' [patent_app_type] => utility [patent_app_number] => 14/903499 [patent_app_country] => US [patent_app_date] => 2014-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 10256 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14903499 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/903499
Device for controlling a power load in an electrical network, and associated method and system Jun 25, 2014 Issued
Array ( [id] => 10314995 [patent_doc_number] => 20150199998 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-07-16 [patent_title] => 'SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 14/314493 [patent_app_country] => US [patent_app_date] => 2014-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 6515 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14314493 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/314493
Semiconductor device Jun 24, 2014 Issued
Array ( [id] => 10184520 [patent_doc_number] => 09214201 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-12-15 [patent_title] => 'DRAM and access and operating method thereof' [patent_app_type] => utility [patent_app_number] => 14/311692 [patent_app_country] => US [patent_app_date] => 2014-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4444 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14311692 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/311692
DRAM and access and operating method thereof Jun 22, 2014 Issued
Array ( [id] => 9787645 [patent_doc_number] => 20140304465 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-10-09 [patent_title] => 'DRAM AND ACCESS AND OPERATING METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 14/311667 [patent_app_country] => US [patent_app_date] => 2014-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4472 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14311667 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/311667
DRAM and access and operating method thereof Jun 22, 2014 Issued
Array ( [id] => 10556814 [patent_doc_number] => 09281016 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-03-08 [patent_title] => '3D stacked semiconductor memory devices with sense amplifier electrically connected to a selecting circuit' [patent_app_type] => utility [patent_app_number] => 14/307196 [patent_app_country] => US [patent_app_date] => 2014-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 15 [patent_no_of_words] => 4647 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14307196 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/307196
3D stacked semiconductor memory devices with sense amplifier electrically connected to a selecting circuit Jun 16, 2014 Issued
Array ( [id] => 9791224 [patent_doc_number] => 20150003168 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-01-01 [patent_title] => 'NON-VOLATILE MEMORY DEVICE WITH IMPROVED READING CIRCUIT' [patent_app_type] => utility [patent_app_number] => 14/305482 [patent_app_country] => US [patent_app_date] => 2014-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6274 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14305482 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/305482
Non-volatile memory device with improved reading circuit Jun 15, 2014 Issued
Array ( [id] => 11246207 [patent_doc_number] => 09472251 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-10-18 [patent_title] => 'Semiconductor device having dummy cell region that are symmetrically disposed about peripheral region' [patent_app_type] => utility [patent_app_number] => 14/304610 [patent_app_country] => US [patent_app_date] => 2014-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 15558 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 258 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14304610 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/304610
Semiconductor device having dummy cell region that are symmetrically disposed about peripheral region Jun 12, 2014 Issued
Array ( [id] => 10877854 [patent_doc_number] => 08902647 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-12-02 [patent_title] => 'Write scheme for charge trapping memory' [patent_app_type] => utility [patent_app_number] => 14/289230 [patent_app_country] => US [patent_app_date] => 2014-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 25 [patent_no_of_words] => 10345 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14289230 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/289230
Write scheme for charge trapping memory May 27, 2014 Issued
Array ( [id] => 10865583 [patent_doc_number] => 08891301 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-11-18 [patent_title] => 'Power drop protection for a data storage device' [patent_app_type] => utility [patent_app_number] => 14/285433 [patent_app_country] => US [patent_app_date] => 2014-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 8229 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14285433 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/285433
Power drop protection for a data storage device May 21, 2014 Issued
Array ( [id] => 10246378 [patent_doc_number] => 20150131374 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-05-14 [patent_title] => 'SEMICONDUCTOR DEVICE AND OPERATING METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 14/284095 [patent_app_country] => US [patent_app_date] => 2014-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5091 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14284095 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/284095
Semiconductor device and method of refresh thereof May 20, 2014 Issued
Array ( [id] => 9628112 [patent_doc_number] => 08797800 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-08-05 [patent_title] => 'Select gate materials having different work functions in non-volatile memory' [patent_app_type] => utility [patent_app_number] => 14/279411 [patent_app_country] => US [patent_app_date] => 2014-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 47 [patent_no_of_words] => 16914 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14279411 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/279411
Select gate materials having different work functions in non-volatile memory May 15, 2014 Issued
Array ( [id] => 9696960 [patent_doc_number] => 20140246645 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-09-04 [patent_title] => 'Arrays Of Nonvolatile Memory Cells And Methods Of Forming Arrays Of Nonvolatile Memory Cells' [patent_app_type] => utility [patent_app_number] => 14/276198 [patent_app_country] => US [patent_app_date] => 2014-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 6784 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14276198 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/276198
Arrays of nonvolatile memory cells and methods of forming arrays of nonvolatile memory cells May 12, 2014 Issued
Array ( [id] => 10010248 [patent_doc_number] => 09053771 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-06-09 [patent_title] => 'Semiconductor system' [patent_app_type] => utility [patent_app_number] => 14/270926 [patent_app_country] => US [patent_app_date] => 2014-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 18 [patent_no_of_words] => 12850 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14270926 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/270926
Semiconductor system May 5, 2014 Issued
Array ( [id] => 10099951 [patent_doc_number] => 09136271 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-09-15 [patent_title] => 'Semiconductor device with one-time programmable memory cell including anti-fuse with metal/polycide gate' [patent_app_type] => utility [patent_app_number] => 14/265742 [patent_app_country] => US [patent_app_date] => 2014-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 4 [patent_no_of_words] => 3095 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 47 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14265742 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/265742
Semiconductor device with one-time programmable memory cell including anti-fuse with metal/polycide gate Apr 29, 2014 Issued
Array ( [id] => 9673459 [patent_doc_number] => 20140237322 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-08-21 [patent_title] => 'STORAGE AT M BITS/CELL DENSITY IN N BITS/CELL ANALOG MEMORY CELL DEVICES, M>N' [patent_app_type] => utility [patent_app_number] => 14/264303 [patent_app_country] => US [patent_app_date] => 2014-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 9776 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14264303 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/264303
Storage at M bits/cell density in N bits/cell analog memory cell devices, M>N Apr 28, 2014 Issued
Array ( [id] => 11775903 [patent_doc_number] => 09384848 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-07-05 [patent_title] => 'Nonvolatile semiconductor memory with dual latch sense amplifier' [patent_app_type] => utility [patent_app_number] => 14/263948 [patent_app_country] => US [patent_app_date] => 2014-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 22 [patent_no_of_words] => 12072 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 213 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14263948 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/263948
Nonvolatile semiconductor memory with dual latch sense amplifier Apr 27, 2014 Issued
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