Search

David Lam

Examiner (ID: 2003, Phone: (571)272-1782 , Office: P/2825 )

Most Active Art Unit
2827
Art Unit(s)
2818, 2827, 2825
Total Applications
2102
Issued Applications
2016
Pending Applications
28
Abandoned Applications
60

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 9489734 [patent_doc_number] => 20140140140 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-05-22 [patent_title] => 'Vertical Nonvolatile Memory Devices and Methods of Operating Same' [patent_app_type] => utility [patent_app_number] => 14/164586 [patent_app_country] => US [patent_app_date] => 2014-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 11778 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14164586 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/164586
Vertical nonvolatile memory devices and methods of operating same Jan 26, 2014 Issued
Array ( [id] => 9447923 [patent_doc_number] => 20140119092 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-05-01 [patent_title] => 'PROGRAMMABLE LSI' [patent_app_type] => utility [patent_app_number] => 14/148049 [patent_app_country] => US [patent_app_date] => 2014-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 32570 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14148049 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/148049
Programmable LSI Jan 5, 2014 Issued
Array ( [id] => 10486676 [patent_doc_number] => 20150371696 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-12-24 [patent_title] => 'MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 14/759073 [patent_app_country] => US [patent_app_date] => 2014-01-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5125 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14759073 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/759073
Memory device including a domain wall and ferromagnetic driver nanowire Jan 1, 2014 Issued
Array ( [id] => 9900193 [patent_doc_number] => 20150055392 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-02-26 [patent_title] => 'Memory Device Having Sequentially Cascading Dices' [patent_app_type] => utility [patent_app_number] => 14/133844 [patent_app_country] => US [patent_app_date] => 2013-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 1352 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14133844 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/133844
Memory device having sequentially cascading dices Dec 18, 2013 Issued
Array ( [id] => 10092839 [patent_doc_number] => 09129665 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-09-08 [patent_title] => 'Dynamic brownout adjustment in a storage device' [patent_app_type] => utility [patent_app_number] => 14/135429 [patent_app_country] => US [patent_app_date] => 2013-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 17182 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14135429 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/135429
Dynamic brownout adjustment in a storage device Dec 18, 2013 Issued
Array ( [id] => 9693583 [patent_doc_number] => 08824200 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-09-02 [patent_title] => 'Nonvolative memory cells programable by phase change' [patent_app_type] => utility [patent_app_number] => 14/109398 [patent_app_country] => US [patent_app_date] => 2013-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 7913 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14109398 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/109398
Nonvolative memory cells programable by phase change Dec 16, 2013 Issued
Array ( [id] => 9595929 [patent_doc_number] => 20140192606 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-07-10 [patent_title] => 'STACKED MEMORY DEVICE, MEMORY SYSTEM INCLUDING THE SAME AND METHOD FOR OPERATING THE SAME' [patent_app_type] => utility [patent_app_number] => 14/103090 [patent_app_country] => US [patent_app_date] => 2013-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 7302 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14103090 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/103090
STACKED MEMORY DEVICE, MEMORY SYSTEM INCLUDING THE SAME AND METHOD FOR OPERATING THE SAME Dec 10, 2013 Abandoned
Array ( [id] => 10232119 [patent_doc_number] => 20150117113 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-04-30 [patent_title] => 'PROGRAMMING SCHEME FOR IMPROVED VOLTAGE DISTRIBUTION IN SOLID-STATE MEMORY' [patent_app_type] => utility [patent_app_number] => 14/102356 [patent_app_country] => US [patent_app_date] => 2013-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5069 [patent_no_of_claims] => 44 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14102356 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/102356
Programming scheme for improved voltage distribution in solid-state memory Dec 9, 2013 Issued
Array ( [id] => 9972760 [patent_doc_number] => 09019784 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-04-28 [patent_title] => 'Data training device' [patent_app_type] => utility [patent_app_number] => 14/100684 [patent_app_country] => US [patent_app_date] => 2013-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6005 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14100684 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/100684
Data training device Dec 8, 2013 Issued
Array ( [id] => 9959640 [patent_doc_number] => 09007854 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2015-04-14 [patent_title] => 'Method and system for optimized soft decoding in a data storage device' [patent_app_type] => utility [patent_app_number] => 14/100404 [patent_app_country] => US [patent_app_date] => 2013-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 20 [patent_no_of_words] => 6513 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14100404 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/100404
Method and system for optimized soft decoding in a data storage device Dec 8, 2013 Issued
Array ( [id] => 9544438 [patent_doc_number] => 20140169085 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-06-19 [patent_title] => 'VOLTAGE-CONTROLLED MAGNETIC MEMORY ELEMENT WITH CANTED MAGNETIZATION' [patent_app_type] => utility [patent_app_number] => 14/101260 [patent_app_country] => US [patent_app_date] => 2013-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 8271 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14101260 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/101260
Voltage-controlled magnetic memory element with canted magnetization Dec 8, 2013 Issued
Array ( [id] => 10035217 [patent_doc_number] => 09076538 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-07-07 [patent_title] => 'Fuse information storage circuit of semiconductor apparatus' [patent_app_type] => utility [patent_app_number] => 14/100168 [patent_app_country] => US [patent_app_date] => 2013-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 2678 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14100168 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/100168
Fuse information storage circuit of semiconductor apparatus Dec 8, 2013 Issued
Array ( [id] => 9544437 [patent_doc_number] => 20140169084 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-06-19 [patent_title] => 'Memory device' [patent_app_type] => utility [patent_app_number] => 14/099174 [patent_app_country] => US [patent_app_date] => 2013-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 8543 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14099174 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/099174
Memory device Dec 5, 2013 Abandoned
Array ( [id] => 10261472 [patent_doc_number] => 20150146470 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-05-28 [patent_title] => 'WRITE ASSIST CIRCUIT FOR WRITE DISTURBED MEMORY CELL' [patent_app_type] => utility [patent_app_number] => 14/089819 [patent_app_country] => US [patent_app_date] => 2013-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5386 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14089819 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/089819
Write assist circuit for write disturbed memory cell Nov 25, 2013 Issued
Array ( [id] => 9368974 [patent_doc_number] => 20140078847 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-03-20 [patent_title] => 'MEMORY REFRESH METHODS, MEMORY SECTION CONTROL CIRCUITS, AND APPARATUSES' [patent_app_type] => utility [patent_app_number] => 14/084417 [patent_app_country] => US [patent_app_date] => 2013-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4817 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14084417 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/084417
Memory refresh methods, memory section control circuits, and apparatuses Nov 18, 2013 Issued
Array ( [id] => 10106483 [patent_doc_number] => 09142266 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-09-22 [patent_title] => 'Memory circuitry using write assist voltage boost' [patent_app_type] => utility [patent_app_number] => 14/083619 [patent_app_country] => US [patent_app_date] => 2013-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3176 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 290 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14083619 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/083619
Memory circuitry using write assist voltage boost Nov 18, 2013 Issued
Array ( [id] => 9945885 [patent_doc_number] => 08995201 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2015-03-31 [patent_title] => 'Methods circuits apparatuses and systems for sensing a logical state of a non-volatile memory cell and non-volatile memory devices produced accordingly' [patent_app_type] => utility [patent_app_number] => 14/073914 [patent_app_country] => US [patent_app_date] => 2013-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 14 [patent_no_of_words] => 8803 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14073914 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/073914
Methods circuits apparatuses and systems for sensing a logical state of a non-volatile memory cell and non-volatile memory devices produced accordingly Nov 6, 2013 Issued
Array ( [id] => 9845984 [patent_doc_number] => 08947911 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2015-02-03 [patent_title] => 'Method and circuit for optimizing bit line power consumption' [patent_app_type] => utility [patent_app_number] => 14/074478 [patent_app_country] => US [patent_app_date] => 2013-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 22 [patent_no_of_words] => 5155 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14074478 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/074478
Method and circuit for optimizing bit line power consumption Nov 6, 2013 Issued
Array ( [id] => 10433459 [patent_doc_number] => 20150318471 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-11-05 [patent_title] => 'STORAGE DEVICE AND STORAGE UNIT' [patent_app_type] => utility [patent_app_number] => 14/647793 [patent_app_country] => US [patent_app_date] => 2013-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 14897 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14647793 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/647793
Storage device and storage unit with ion source layer and resistance change layer Nov 5, 2013 Issued
Array ( [id] => 9877173 [patent_doc_number] => 08964454 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2015-02-24 [patent_title] => 'Three-dimensional static random access memory cell' [patent_app_type] => utility [patent_app_number] => 14/071832 [patent_app_country] => US [patent_app_date] => 2013-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 4616 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14071832 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/071832
Three-dimensional static random access memory cell Nov 4, 2013 Issued
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