
David Lam
Examiner (ID: 19604)
| Most Active Art Unit | 2827 |
| Art Unit(s) | 2818, 2827, 2825 |
| Total Applications | 2102 |
| Issued Applications | 2016 |
| Pending Applications | 28 |
| Abandoned Applications | 60 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 10839585
[patent_doc_number] => 08867270
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2014-10-21
[patent_title] => 'Method for performing memory access management, and associated memory device and controller thereof'
[patent_app_type] => utility
[patent_app_number] => 13/944866
[patent_app_country] => US
[patent_app_date] => 2013-07-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 10
[patent_no_of_words] => 10633
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 156
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13944866
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/944866 | Method for performing memory access management, and associated memory device and controller thereof | Jul 16, 2013 | Issued |
Array
(
[id] => 9553889
[patent_doc_number] => 08760949
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2014-06-24
[patent_title] => 'Mechanisms for built-in self repair of memory devices using failed bit maps and obvious repairs'
[patent_app_type] => utility
[patent_app_number] => 13/942040
[patent_app_country] => US
[patent_app_date] => 2013-07-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 7157
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 87
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13942040
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/942040 | Mechanisms for built-in self repair of memory devices using failed bit maps and obvious repairs | Jul 14, 2013 | Issued |
Array
(
[id] => 9146833
[patent_doc_number] => 20130301356
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-11-14
[patent_title] => 'SEMICONDUCTOR DEVICE WITH ONE-TIME PROGRAMMABLE MEMORY CELL INCLUDING ANTI-FUSE WITH MAETAL/POLYCIDE GATE'
[patent_app_type] => utility
[patent_app_number] => 13/941120
[patent_app_country] => US
[patent_app_date] => 2013-07-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 3066
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13941120
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/941120 | Semiconductor device with one-time programmable memory cell including anti-fuse with metal/polycide gate | Jul 11, 2013 | Issued |
Array
(
[id] => 10839611
[patent_doc_number] => 08867297
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2014-10-21
[patent_title] => 'Charge/discharge control circuit and charge/discharge method thereof'
[patent_app_type] => utility
[patent_app_number] => 13/938254
[patent_app_country] => US
[patent_app_date] => 2013-07-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 3839
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 134
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13938254
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/938254 | Charge/discharge control circuit and charge/discharge method thereof | Jul 9, 2013 | Issued |
Array
(
[id] => 9650410
[patent_doc_number] => 08804436
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2014-08-12
[patent_title] => 'Method of partial refresh during erase operation'
[patent_app_type] => utility
[patent_app_number] => 13/937804
[patent_app_country] => US
[patent_app_date] => 2013-07-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 4460
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 162
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13937804
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/937804 | Method of partial refresh during erase operation | Jul 8, 2013 | Issued |
Array
(
[id] => 9804229
[patent_doc_number] => 20150016174
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-01-15
[patent_title] => 'INTEGRATED CIRCUITS WITH PROGRAMMABLE ELECTRICAL CONNECTIONS AND METHODS FOR FABRICATING THE SAME'
[patent_app_type] => utility
[patent_app_number] => 13/937962
[patent_app_country] => US
[patent_app_date] => 2013-07-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 5594
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13937962
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/937962 | Integrated circuits with programmable electrical connections and methods for fabricating the same | Jul 8, 2013 | Issued |
Array
(
[id] => 9346473
[patent_doc_number] => 08665627
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2014-03-04
[patent_title] => 'Built-in self test for one-time-programmable memory'
[patent_app_type] => utility
[patent_app_number] => 13/936313
[patent_app_country] => US
[patent_app_date] => 2013-07-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 4646
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 112
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13936313
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/936313 | Built-in self test for one-time-programmable memory | Jul 7, 2013 | Issued |
Array
(
[id] => 10041792
[patent_doc_number] => 09082504
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2015-07-14
[patent_title] => 'Semiconductor memory device storing refresh period information and operating method thereof'
[patent_app_type] => utility
[patent_app_number] => 13/936057
[patent_app_country] => US
[patent_app_date] => 2013-07-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 19
[patent_no_of_words] => 9955
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 94
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13936057
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/936057 | Semiconductor memory device storing refresh period information and operating method thereof | Jul 4, 2013 | Issued |
Array
(
[id] => 9377280
[patent_doc_number] => 08681550
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2014-03-25
[patent_title] => 'Error recovery for flash memory'
[patent_app_type] => utility
[patent_app_number] => 13/933986
[patent_app_country] => US
[patent_app_date] => 2013-07-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 16
[patent_no_of_words] => 6912
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 120
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13933986
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/933986 | Error recovery for flash memory | Jul 1, 2013 | Issued |
Array
(
[id] => 9210819
[patent_doc_number] => 20140009996
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-01-09
[patent_title] => 'STORAGE CONTROL DEVICE, STORAGE DEVICE, INFORMATION PROCESSING SYSTEM, AND PROCESSING METHOD THEREOF'
[patent_app_type] => utility
[patent_app_number] => 13/928472
[patent_app_country] => US
[patent_app_date] => 2013-06-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 14
[patent_no_of_words] => 7967
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13928472
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/928472 | STORAGE CONTROL DEVICE, STORAGE DEVICE, INFORMATION PROCESSING SYSTEM, AND PROCESSING METHOD THEREOF | Jun 26, 2013 | Abandoned |
Array
(
[id] => 9705669
[patent_doc_number] => 08830750
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2014-09-09
[patent_title] => 'Data reading method, and control circuit, memory module and memory storage apparatus using the same'
[patent_app_type] => utility
[patent_app_number] => 13/928356
[patent_app_country] => US
[patent_app_date] => 2013-06-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 18
[patent_no_of_words] => 10645
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 299
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13928356
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/928356 | Data reading method, and control circuit, memory module and memory storage apparatus using the same | Jun 25, 2013 | Issued |
Array
(
[id] => 9119819
[patent_doc_number] => 20130286741
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-10-31
[patent_title] => 'OVER-SAMPLING READ OPERATION FOR A FLASH MEMORY DEVICE'
[patent_app_type] => utility
[patent_app_number] => 13/926297
[patent_app_country] => US
[patent_app_date] => 2013-06-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 4062
[patent_no_of_claims] => 1
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13926297
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/926297 | Over-sampling read operation for a flash memory device | Jun 24, 2013 | Issued |
Array
(
[id] => 9123709
[patent_doc_number] => 20130290631
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-10-31
[patent_title] => 'CONVERTING LUNS INTO FILES OR FILES INTO LUNS IN REAL TIME'
[patent_app_type] => utility
[patent_app_number] => 13/925228
[patent_app_country] => US
[patent_app_date] => 2013-06-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 14
[patent_no_of_words] => 11369
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13925228
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/925228 | Converting LUNs into files or files into LUNs in real time | Jun 23, 2013 | Issued |
Array
(
[id] => 9640908
[patent_doc_number] => 20140219019
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-08-07
[patent_title] => 'SOLID STATE DRIVE AND DATA ERASING METHOD THEREOF'
[patent_app_type] => utility
[patent_app_number] => 13/920159
[patent_app_country] => US
[patent_app_date] => 2013-06-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 3726
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13920159
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/920159 | Solid state drive and data erasing method thereof | Jun 17, 2013 | Issued |
Array
(
[id] => 9106108
[patent_doc_number] => 20130279240
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-10-24
[patent_title] => 'HETERO-SWITCHING LAYER IN A RRAM DEVICE AND METHOD'
[patent_app_type] => utility
[patent_app_number] => 13/920021
[patent_app_country] => US
[patent_app_date] => 2013-06-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 9230
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13920021
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/920021 | Hetero-switching layer in a RRAM device and method | Jun 16, 2013 | Issued |
Array
(
[id] => 9577064
[patent_doc_number] => 08767491
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2014-07-01
[patent_title] => 'Apparatus and method for remapping addresses of defective memory locations to redundant memory locations'
[patent_app_type] => utility
[patent_app_number] => 13/913676
[patent_app_country] => US
[patent_app_date] => 2013-06-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 23
[patent_no_of_words] => 6928
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 137
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13913676
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/913676 | Apparatus and method for remapping addresses of defective memory locations to redundant memory locations | Jun 9, 2013 | Issued |
Array
(
[id] => 9146818
[patent_doc_number] => 20130301341
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-11-14
[patent_title] => 'HERETO RESISTIVE SWITCHING MATERIAL LAYER IN RRAM DEVICE AND METHOD'
[patent_app_type] => utility
[patent_app_number] => 13/905074
[patent_app_country] => US
[patent_app_date] => 2013-05-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 8790
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13905074
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/905074 | Hereto resistive switching material layer in RRAM device and method | May 28, 2013 | Issued |
Array
(
[id] => 9052967
[patent_doc_number] => 20130250681
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-09-26
[patent_title] => 'NONVOLATILE SEMICONDUCTOR MEMORY'
[patent_app_type] => utility
[patent_app_number] => 13/899843
[patent_app_country] => US
[patent_app_date] => 2013-05-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 20
[patent_figures_cnt] => 20
[patent_no_of_words] => 12111
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13899843
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/899843 | Nonvolatile semiconductor memory | May 21, 2013 | Issued |
Array
(
[id] => 9052977
[patent_doc_number] => 20130250691
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-09-26
[patent_title] => 'METHOD OF PROVIDING AN OPERATING VOLTAGE IN A MEMORY DEVICE AND A MEMORY CONTROLLER FOR THE MEMORY DEVICE'
[patent_app_type] => utility
[patent_app_number] => 13/892427
[patent_app_country] => US
[patent_app_date] => 2013-05-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 15
[patent_no_of_words] => 5842
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13892427
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/892427 | METHOD OF PROVIDING AN OPERATING VOLTAGE IN A MEMORY DEVICE AND A MEMORY CONTROLLER FOR THE MEMORY DEVICE | May 12, 2013 | Abandoned |
Array
(
[id] => 10877865
[patent_doc_number] => 08902657
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2014-12-02
[patent_title] => 'Semiconductor memory device and controller'
[patent_app_type] => utility
[patent_app_number] => 13/837814
[patent_app_country] => US
[patent_app_date] => 2013-03-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 54
[patent_figures_cnt] => 73
[patent_no_of_words] => 23672
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 96
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13837814
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/837814 | Semiconductor memory device and controller | Mar 14, 2013 | Issued |