Search

David Lam

Examiner (ID: 2003, Phone: (571)272-1782 , Office: P/2825 )

Most Active Art Unit
2827
Art Unit(s)
2818, 2827, 2825
Total Applications
2102
Issued Applications
2016
Pending Applications
28
Abandoned Applications
60

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 9640917 [patent_doc_number] => 20140219028 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-08-07 [patent_title] => 'Compensation Loop for Read Voltage Adaptation' [patent_app_type] => utility [patent_app_number] => 13/757027 [patent_app_country] => US [patent_app_date] => 2013-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3320 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13757027 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/757027
Compensation loop for read voltage adaptation Jan 31, 2013 Issued
Array ( [id] => 10859198 [patent_doc_number] => 08885405 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-11-11 [patent_title] => 'Flash memory and associated programming method' [patent_app_type] => utility [patent_app_number] => 13/755045 [patent_app_country] => US [patent_app_date] => 2013-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 5452 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13755045 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/755045
Flash memory and associated programming method Jan 30, 2013 Issued
Array ( [id] => 9475767 [patent_doc_number] => 20140133230 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-05-15 [patent_title] => 'BIT LINE RESISTANCE COMPENSATION' [patent_app_type] => utility [patent_app_number] => 13/755905 [patent_app_country] => US [patent_app_date] => 2013-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 20331 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13755905 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/755905
Bit line resistance compensation Jan 30, 2013 Issued
Array ( [id] => 9614802 [patent_doc_number] => 20140204659 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-07-24 [patent_title] => 'CAPACITIVE COUPLED SENSE AMPLIFIER BIASED AT MAXIMUM GAIN POINT' [patent_app_type] => utility [patent_app_number] => 13/746653 [patent_app_country] => US [patent_app_date] => 2013-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7551 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13746653 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/746653
Capacitive coupled sense amplifier biased at maximum gain point Jan 21, 2013 Issued
Array ( [id] => 9402105 [patent_doc_number] => 08692158 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-04-08 [patent_title] => 'Portable weld cooling systems' [patent_app_type] => utility [patent_app_number] => 13/743290 [patent_app_country] => US [patent_app_date] => 2013-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6957 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13743290 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/743290
Portable weld cooling systems Jan 15, 2013 Issued
Array ( [id] => 8915138 [patent_doc_number] => 20130176763 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-07-11 [patent_title] => 'STACKED MEMORY WITH REDUNDANCY' [patent_app_type] => utility [patent_app_number] => 13/728330 [patent_app_country] => US [patent_app_date] => 2012-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 6468 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13728330 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/728330
Stacked memory with redundancy Dec 26, 2012 Issued
Array ( [id] => 8915182 [patent_doc_number] => 20130176807 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-07-11 [patent_title] => 'DRAM AND ACCESS AND OPERATING METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 13/728134 [patent_app_country] => US [patent_app_date] => 2012-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4442 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13728134 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/728134
DRAM and access and operating method thereof Dec 26, 2012 Issued
Array ( [id] => 10865556 [patent_doc_number] => 08891273 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-11-18 [patent_title] => 'Pseudo-NOR cell for ternary content addressable memory' [patent_app_type] => utility [patent_app_number] => 13/727494 [patent_app_country] => US [patent_app_date] => 2012-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6518 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13727494 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/727494
Pseudo-NOR cell for ternary content addressable memory Dec 25, 2012 Issued
Array ( [id] => 9337162 [patent_doc_number] => 20140063944 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-03-06 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME' [patent_app_type] => utility [patent_app_number] => 13/726924 [patent_app_country] => US [patent_app_date] => 2012-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4120 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13726924 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/726924
Semiconductor memory device and method of operating the same Dec 25, 2012 Issued
Array ( [id] => 10839604 [patent_doc_number] => 08867289 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-10-21 [patent_title] => 'Chip with embedded non-volatile memory and testing method therefor' [patent_app_type] => utility [patent_app_number] => 13/727046 [patent_app_country] => US [patent_app_date] => 2012-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3183 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13727046 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/727046
Chip with embedded non-volatile memory and testing method therefor Dec 25, 2012 Issued
Array ( [id] => 9559644 [patent_doc_number] => 20140177356 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-06-26 [patent_title] => 'PROGRAMMABLE RESISTANCE-MODULATED WRITE ASSIST FOR A MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 13/726800 [patent_app_country] => US [patent_app_date] => 2012-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 9126 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13726800 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/726800
Programmable resistance-modulated write assist for a memory device Dec 25, 2012 Issued
Array ( [id] => 9559647 [patent_doc_number] => 20140177359 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-06-26 [patent_title] => 'METHOD AND APPARATUS FOR ALIGNING A CLOCK SIGNAL AND A DATA STROBE SIGNAL IN A MEMORY SYSTEM' [patent_app_type] => utility [patent_app_number] => 13/726392 [patent_app_country] => US [patent_app_date] => 2012-12-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 6650 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13726392 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/726392
Method and apparatus for aligning a clock signal and a data strobe signal in a memory system Dec 23, 2012 Issued
Array ( [id] => 8852319 [patent_doc_number] => 20130141994 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-06-06 [patent_title] => 'SEMICONDUCTOR DEVICE HAVING SKEW DETECTION CIRCUIT MEASURING SKEW BETWEEN CLOCK SIGNAL AND DATA STROBE SIGNAL' [patent_app_type] => utility [patent_app_number] => 13/693834 [patent_app_country] => US [patent_app_date] => 2012-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 10167 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13693834 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/693834
Semiconductor device having skew detection circuit measuring skew between clock signal and data strobe signal Dec 3, 2012 Issued
Array ( [id] => 10884038 [patent_doc_number] => 08908426 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-12-09 [patent_title] => 'Cell sensing circuit for phase change memory and methods thereof' [patent_app_type] => utility [patent_app_number] => 13/693816 [patent_app_country] => US [patent_app_date] => 2012-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 18 [patent_no_of_words] => 4657 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13693816 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/693816
Cell sensing circuit for phase change memory and methods thereof Dec 3, 2012 Issued
Array ( [id] => 9516850 [patent_doc_number] => 20140153341 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-06-05 [patent_title] => 'SEQUENTIAL ACCESS MEMORY WITH MASTER-SLAVE LATCH PAIRS AND METHOD OF OPERATING' [patent_app_type] => utility [patent_app_number] => 13/693808 [patent_app_country] => US [patent_app_date] => 2012-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 5554 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13693808 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/693808
Sequential access memory with master-slave latch pairs and method of operating Dec 3, 2012 Issued
Array ( [id] => 9705668 [patent_doc_number] => 08830749 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-09-09 [patent_title] => 'Semiconductor memory device and method for controlling the same' [patent_app_type] => utility [patent_app_number] => 13/692986 [patent_app_country] => US [patent_app_date] => 2012-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4522 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13692986 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/692986
Semiconductor memory device and method for controlling the same Dec 2, 2012 Issued
Array ( [id] => 9337173 [patent_doc_number] => 20140063955 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-03-06 [patent_title] => 'STORAGE DEVICE AND CONTROL METHOD OF NONVOLATILE MEMORY' [patent_app_type] => utility [patent_app_number] => 13/692076 [patent_app_country] => US [patent_app_date] => 2012-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 8484 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13692076 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/692076
Storage device and control method of nonvolatile memory Dec 2, 2012 Issued
Array ( [id] => 9531344 [patent_doc_number] => 08755226 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-06-17 [patent_title] => 'Storage device and control method of nonvolatile memory' [patent_app_type] => utility [patent_app_number] => 13/692106 [patent_app_country] => US [patent_app_date] => 2012-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 19 [patent_no_of_words] => 5664 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13692106 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/692106
Storage device and control method of nonvolatile memory Dec 2, 2012 Issued
Array ( [id] => 9828597 [patent_doc_number] => 08937829 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-01-20 [patent_title] => 'System and a method for designing a hybrid memory cell with memristor and complementary metal-oxide semiconductor' [patent_app_type] => utility [patent_app_number] => 13/691830 [patent_app_country] => US [patent_app_date] => 2012-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7559 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13691830 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/691830
System and a method for designing a hybrid memory cell with memristor and complementary metal-oxide semiconductor Dec 1, 2012 Issued
Array ( [id] => 9952757 [patent_doc_number] => 09001557 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-04-07 [patent_title] => 'Variable resistance nonvolatile memory element writing method and variable resistance nonvolatile memory device' [patent_app_type] => utility [patent_app_number] => 13/990209 [patent_app_country] => US [patent_app_date] => 2012-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 24 [patent_no_of_words] => 20369 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 301 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13990209 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/990209
Variable resistance nonvolatile memory element writing method and variable resistance nonvolatile memory device Nov 20, 2012 Issued
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