Search

David Lam

Examiner (ID: 2003, Phone: (571)272-1782 , Office: P/2825 )

Most Active Art Unit
2827
Art Unit(s)
2818, 2827, 2825
Total Applications
2102
Issued Applications
2016
Pending Applications
28
Abandoned Applications
60

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 8380788 [patent_doc_number] => 20120224417 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-09-06 [patent_title] => 'DIODE ASSISTED SWITCHING SPIN-TRANSFER TORQUE MEMORY UNIT' [patent_app_type] => utility [patent_app_number] => 13/472867 [patent_app_country] => US [patent_app_date] => 2012-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4673 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13472867 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/472867
Diode assisted switching spin-transfer torque memory unit May 15, 2012 Issued
Array ( [id] => 9155095 [patent_doc_number] => 08588005 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-11-19 [patent_title] => 'Buffering systems for accessing multiple layers of memory in integrated circuits' [patent_app_type] => utility [patent_app_number] => 13/455018 [patent_app_country] => US [patent_app_date] => 2012-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 17 [patent_no_of_words] => 7972 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 249 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13455018 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/455018
Buffering systems for accessing multiple layers of memory in integrated circuits Apr 23, 2012 Issued
Array ( [id] => 8349126 [patent_doc_number] => 20120210052 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-08-16 [patent_title] => 'INTEGRATED CIRCUIT WITH COMPRESS ENGINE' [patent_app_type] => utility [patent_app_number] => 13/454996 [patent_app_country] => US [patent_app_date] => 2012-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 13147 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13454996 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/454996
INTEGRATED CIRCUIT WITH COMPRESS ENGINE Apr 23, 2012 Abandoned
Array ( [id] => 9061299 [patent_doc_number] => 08547742 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-10-01 [patent_title] => 'Storage at M bits/cell density in N bits/cell analog memory cell devices, M>N' [patent_app_type] => utility [patent_app_number] => 13/449326 [patent_app_country] => US [patent_app_date] => 2012-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 9830 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13449326 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/449326
Storage at M bits/cell density in N bits/cell analog memory cell devices, M>N Apr 17, 2012 Issued
Array ( [id] => 8957438 [patent_doc_number] => 08503224 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-08-06 [patent_title] => 'Spintronic devices with integrated transistors' [patent_app_type] => utility [patent_app_number] => 13/448076 [patent_app_country] => US [patent_app_date] => 2012-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 7536 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 38 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13448076 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/448076
Spintronic devices with integrated transistors Apr 15, 2012 Issued
Array ( [id] => 10073239 [patent_doc_number] => 09111600 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-08-18 [patent_title] => 'Memory cell with improved write margin' [patent_app_type] => utility [patent_app_number] => 13/997633 [patent_app_country] => US [patent_app_date] => 2012-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 9550 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13997633 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/997633
Memory cell with improved write margin Mar 29, 2012 Issued
Array ( [id] => 9023390 [patent_doc_number] => 08533387 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-09-10 [patent_title] => 'Interface for solid-state memory' [patent_app_type] => utility [patent_app_number] => 13/431059 [patent_app_country] => US [patent_app_date] => 2012-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6670 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13431059 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/431059
Interface for solid-state memory Mar 26, 2012 Issued
Array ( [id] => 8466855 [patent_doc_number] => 20120272024 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-10-25 [patent_title] => 'DATA STORAGE SYSTEM AND A DATA RETENTION METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 13/431536 [patent_app_country] => US [patent_app_date] => 2012-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 5845 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13431536 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/431536
Data storage system and a data retention method thereof Mar 26, 2012 Issued
Array ( [id] => 9052974 [patent_doc_number] => 20130250688 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-09-26 [patent_title] => 'SELECTED WORD LINE DEPENDENT PROGRAMMING VOLTAGE' [patent_app_type] => utility [patent_app_number] => 13/430480 [patent_app_country] => US [patent_app_date] => 2012-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 29 [patent_no_of_words] => 26093 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13430480 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/430480
Selected word line dependent programming voltage Mar 25, 2012 Issued
Array ( [id] => 8418918 [patent_doc_number] => 20120246418 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-09-27 [patent_title] => 'MEMORY ARCHITECTURE FOR DISPLAY DEVICE AND CONTROL METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 13/428002 [patent_app_country] => US [patent_app_date] => 2012-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4039 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13428002 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/428002
Memory architecture for display device and control method thereof Mar 22, 2012 Issued
Array ( [id] => 9141867 [patent_doc_number] => 08582341 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-11-12 [patent_title] => 'Semiconductor device and method for manufacturing same' [patent_app_type] => utility [patent_app_number] => 13/424552 [patent_app_country] => US [patent_app_date] => 2012-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 29 [patent_no_of_words] => 6691 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13424552 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/424552
Semiconductor device and method for manufacturing same Mar 19, 2012 Issued
Array ( [id] => 8276529 [patent_doc_number] => 20120170395 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-07-05 [patent_title] => 'Data Flow Control in Multiple Independent Port' [patent_app_type] => utility [patent_app_number] => 13/418478 [patent_app_country] => US [patent_app_date] => 2012-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 16281 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13418478 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/418478
Data flow control in multiple independent port Mar 12, 2012 Issued
Array ( [id] => 8935603 [patent_doc_number] => 08495320 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-07-23 [patent_title] => 'Method and apparatus for storing data in a flash memory including single level memory cells and multi level memory cells' [patent_app_type] => utility [patent_app_number] => 13/416678 [patent_app_country] => US [patent_app_date] => 2012-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 13 [patent_no_of_words] => 7133 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13416678 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/416678
Method and apparatus for storing data in a flash memory including single level memory cells and multi level memory cells Mar 8, 2012 Issued
Array ( [id] => 8263670 [patent_doc_number] => 20120163099 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-06-28 [patent_title] => 'MODE-REGISTER READING CONTROLLER AND SEMICONDUCTOR MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 13/410833 [patent_app_country] => US [patent_app_date] => 2012-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3032 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13410833 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/410833
Mode-register reading controller and semiconductor memory device Mar 1, 2012 Issued
Array ( [id] => 8238934 [patent_doc_number] => 20120147671 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-06-14 [patent_title] => 'OVER-SAMPLING READ OPERATION FOR A FLASH MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 13/402922 [patent_app_country] => US [patent_app_date] => 2012-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4033 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13402922 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/402922
Over-sampling read operation for a flash memory device Feb 22, 2012 Issued
Array ( [id] => 9403204 [patent_doc_number] => 08693264 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-04-08 [patent_title] => 'Memory device having sensing circuitry with automatic latching of sense amplifier output node' [patent_app_type] => utility [patent_app_number] => 13/400864 [patent_app_country] => US [patent_app_date] => 2012-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 4591 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 26 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13400864 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/400864
Memory device having sensing circuitry with automatic latching of sense amplifier output node Feb 20, 2012 Issued
Array ( [id] => 8346063 [patent_doc_number] => 20120206979 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-08-16 [patent_title] => '3-D STRUCTURED NON-VOLATILE MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 13/397024 [patent_app_country] => US [patent_app_date] => 2012-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 6483 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13397024 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/397024
3-D structured non-volatile memory device and method of manufacturing the same Feb 14, 2012 Issued
Array ( [id] => 9346496 [patent_doc_number] => 08665650 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-03-04 [patent_title] => 'Reliability metrics management for soft decoding' [patent_app_type] => utility [patent_app_number] => 13/397434 [patent_app_country] => US [patent_app_date] => 2012-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7354 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 230 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13397434 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/397434
Reliability metrics management for soft decoding Feb 14, 2012 Issued
Array ( [id] => 8369420 [patent_doc_number] => 20120218809 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-08-30 [patent_title] => 'STORAGE APPARATUS AND OPERATION METHOD FOR OPERATING THE SAME' [patent_app_type] => utility [patent_app_number] => 13/397282 [patent_app_country] => US [patent_app_date] => 2012-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 15397 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13397282 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/397282
Storage apparatus and operation method for operating the same Feb 14, 2012 Issued
Array ( [id] => 9484747 [patent_doc_number] => 08730704 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-05-20 [patent_title] => 'Content addressable memory array having local interconnects' [patent_app_type] => utility [patent_app_number] => 13/371236 [patent_app_country] => US [patent_app_date] => 2012-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 6239 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13371236 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/371236
Content addressable memory array having local interconnects Feb 9, 2012 Issued
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