Search

David Lam

Examiner (ID: 19604)

Most Active Art Unit
2827
Art Unit(s)
2818, 2827, 2825
Total Applications
2102
Issued Applications
2016
Pending Applications
28
Abandoned Applications
60

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4500827 [patent_doc_number] => 07957199 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-06-07 [patent_title] => 'Method of erasing in non-volatile memory device' [patent_app_type] => utility [patent_app_number] => 12/833098 [patent_app_country] => US [patent_app_date] => 2010-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 5559 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/957/07957199.pdf [firstpage_image] =>[orig_patent_app_number] => 12833098 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/833098
Method of erasing in non-volatile memory device Jul 8, 2010 Issued
Array ( [id] => 6337525 [patent_doc_number] => 20100329018 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-12-30 [patent_title] => 'METHOD OF OPERATING NONVOLATILE MEMORY DEVICE CAPABLE OF READING TWO PLANES' [patent_app_type] => utility [patent_app_number] => 12/826936 [patent_app_country] => US [patent_app_date] => 2010-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4347 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0329/20100329018.pdf [firstpage_image] =>[orig_patent_app_number] => 12826936 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/826936
Method of operating nonvolatile memory device capable of reading two planes Jun 29, 2010 Issued
Array ( [id] => 6337564 [patent_doc_number] => 20100329022 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-12-30 [patent_title] => 'METHOD OF PROGRAMMING NONVOLATILE MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 12/827754 [patent_app_country] => US [patent_app_date] => 2010-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4768 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0329/20100329022.pdf [firstpage_image] =>[orig_patent_app_number] => 12827754 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/827754
Method of programming nonvolatile memory device Jun 29, 2010 Issued
Array ( [id] => 6140583 [patent_doc_number] => 20110128811 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-06-02 [patent_title] => 'INTERNAL COMMAND GENERATION CIRCUIT' [patent_app_type] => utility [patent_app_number] => 12/826906 [patent_app_country] => US [patent_app_date] => 2010-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4054 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0128/20110128811.pdf [firstpage_image] =>[orig_patent_app_number] => 12826906 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/826906
Internal command generation circuit Jun 29, 2010 Issued
Array ( [id] => 5957714 [patent_doc_number] => 20110182101 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-07-28 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE WITH SECURITY FUNCTION AND CONTROL METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 12/827780 [patent_app_country] => US [patent_app_date] => 2010-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5089 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0182/20110182101.pdf [firstpage_image] =>[orig_patent_app_number] => 12827780 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/827780
Semiconductor memory device with security function and control method thereof Jun 29, 2010 Issued
Array ( [id] => 6337674 [patent_doc_number] => 20100329037 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-12-30 [patent_title] => 'CIRCUIT FOR SUPPLYING WELL VOLTAGES IN NONVOLATILE MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 12/826978 [patent_app_country] => US [patent_app_date] => 2010-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4912 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0329/20100329037.pdf [firstpage_image] =>[orig_patent_app_number] => 12826978 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/826978
Circuit for supplying well voltages in nonvolatile memory device Jun 29, 2010 Issued
Array ( [id] => 6157430 [patent_doc_number] => 20110158022 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-06-30 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE HAVING A REDUCED NOISE INTERFERENCE' [patent_app_type] => utility [patent_app_number] => 12/826918 [patent_app_country] => US [patent_app_date] => 2010-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3046 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0158/20110158022.pdf [firstpage_image] =>[orig_patent_app_number] => 12826918 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/826918
Semiconductor memory device having a reduced noise interference Jun 29, 2010 Issued
Array ( [id] => 4503954 [patent_doc_number] => 07948818 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-05-24 [patent_title] => 'Memory repair system and method' [patent_app_type] => utility [patent_app_number] => 12/827446 [patent_app_country] => US [patent_app_date] => 2010-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 23 [patent_no_of_words] => 9100 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/948/07948818.pdf [firstpage_image] =>[orig_patent_app_number] => 12827446 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/827446
Memory repair system and method Jun 29, 2010 Issued
Array ( [id] => 7708849 [patent_doc_number] => 20120002471 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-01-05 [patent_title] => 'Memory Bit Redundant Vias' [patent_app_type] => utility [patent_app_number] => 12/827084 [patent_app_country] => US [patent_app_date] => 2010-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3944 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12827084 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/827084
Memory bit redundant vias Jun 29, 2010 Issued
Array ( [id] => 6093259 [patent_doc_number] => 20110002182 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-01-06 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR OPERATING THE SAME' [patent_app_type] => utility [patent_app_number] => 12/827530 [patent_app_country] => US [patent_app_date] => 2010-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4632 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0002/20110002182.pdf [firstpage_image] =>[orig_patent_app_number] => 12827530 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/827530
Semiconductor memory device and method for operating the same Jun 29, 2010 Issued
Array ( [id] => 6537454 [patent_doc_number] => 20100232222 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-09-16 [patent_title] => 'MEMORY PAGE BOOSTING METHOD, DEVICE AND SYSTEM' [patent_app_type] => utility [patent_app_number] => 12/787601 [patent_app_country] => US [patent_app_date] => 2010-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 8276 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0232/20100232222.pdf [firstpage_image] =>[orig_patent_app_number] => 12787601 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/787601
Memory page boosting method, device and system May 25, 2010 Issued
Array ( [id] => 4480843 [patent_doc_number] => 07869271 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-01-11 [patent_title] => 'Method of testing PRAM device' [patent_app_type] => utility [patent_app_number] => 12/787571 [patent_app_country] => US [patent_app_date] => 2010-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3787 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/869/07869271.pdf [firstpage_image] =>[orig_patent_app_number] => 12787571 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/787571
Method of testing PRAM device May 25, 2010 Issued
Array ( [id] => 8318557 [patent_doc_number] => 08233344 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-07-31 [patent_title] => 'Semiconductor device' [patent_app_type] => utility [patent_app_number] => 12/783918 [patent_app_country] => US [patent_app_date] => 2010-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 9041 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12783918 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/783918
Semiconductor device May 19, 2010 Issued
Array ( [id] => 6602990 [patent_doc_number] => 20100309734 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-12-09 [patent_title] => 'METHOD, SYSTEM, COMPUTER PROGRAM PRODUCT, AND DATA PROCESSING DEVICE FOR MONITORING MEMORY CIRCUITS AND CORRESPONDING INTEGRATED CIRCUIT' [patent_app_type] => utility [patent_app_number] => 12/784164 [patent_app_country] => US [patent_app_date] => 2010-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4387 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0309/20100309734.pdf [firstpage_image] =>[orig_patent_app_number] => 12784164 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/784164
Method, system, computer program product, and data processing device for monitoring memory circuits and corresponding integrated circuit May 19, 2010 Issued
Array ( [id] => 8117295 [patent_doc_number] => 08159863 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-04-17 [patent_title] => '6T SRAM cell with single sided write' [patent_app_type] => utility [patent_app_number] => 12/782874 [patent_app_country] => US [patent_app_date] => 2010-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 19095 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 236 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/159/08159863.pdf [firstpage_image] =>[orig_patent_app_number] => 12782874 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/782874
6T SRAM cell with single sided write May 18, 2010 Issued
Array ( [id] => 8147930 [patent_doc_number] => 08164945 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-04-24 [patent_title] => '8T SRAM cell with two single sided ports' [patent_app_type] => utility [patent_app_number] => 12/782902 [patent_app_country] => US [patent_app_date] => 2010-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 10027 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 204 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/164/08164945.pdf [firstpage_image] =>[orig_patent_app_number] => 12782902 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/782902
8T SRAM cell with two single sided ports May 18, 2010 Issued
Array ( [id] => 6259230 [patent_doc_number] => 20100296335 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-11-25 [patent_title] => 'Asymmetric SRAM Cell with Split Transistors on the Strong Side' [patent_app_type] => utility [patent_app_number] => 12/782894 [patent_app_country] => US [patent_app_date] => 2010-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7534 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0296/20100296335.pdf [firstpage_image] =>[orig_patent_app_number] => 12782894 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/782894
Asymmetric SRAM cell with split transistors on the strong side May 18, 2010 Issued
Array ( [id] => 8179897 [patent_doc_number] => 08179715 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-05-15 [patent_title] => '8T SRAM cell with four load transistors' [patent_app_type] => utility [patent_app_number] => 12/782908 [patent_app_country] => US [patent_app_date] => 2010-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 7895 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 286 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/179/08179715.pdf [firstpage_image] =>[orig_patent_app_number] => 12782908 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/782908
8T SRAM cell with four load transistors May 18, 2010 Issued
Array ( [id] => 8387495 [patent_doc_number] => 08264897 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-09-11 [patent_title] => 'SRAM and method for accessing SRAM' [patent_app_type] => utility [patent_app_number] => 12/782490 [patent_app_country] => US [patent_app_date] => 2010-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 14 [patent_no_of_words] => 8096 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12782490 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/782490
SRAM and method for accessing SRAM May 17, 2010 Issued
Array ( [id] => 8387499 [patent_doc_number] => 08264903 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-09-11 [patent_title] => 'Systems and methods for refreshing a memory module' [patent_app_type] => utility [patent_app_number] => 12/774632 [patent_app_country] => US [patent_app_date] => 2010-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 15991 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12774632 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/774632
Systems and methods for refreshing a memory module May 4, 2010 Issued
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