Search

David Lam

Examiner (ID: 14034, Phone: (571)272-1782 , Office: P/2825 )

Most Active Art Unit
2827
Art Unit(s)
2825, 2827, 2818
Total Applications
2102
Issued Applications
2016
Pending Applications
28
Abandoned Applications
60

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 8204587 [patent_doc_number] => 08189392 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-05-29 [patent_title] => 'Page buffer circuit' [patent_app_type] => utility [patent_app_number] => 12/647609 [patent_app_country] => US [patent_app_date] => 2009-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5268 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/189/08189392.pdf [firstpage_image] =>[orig_patent_app_number] => 12647609 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/647609
Page buffer circuit Dec 27, 2009 Issued
Array ( [id] => 6491809 [patent_doc_number] => 20100214849 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-08-26 [patent_title] => 'PAGE BUFFER CIRCUIT OF NONVOLATILE MEMORY DEVICE AND METHOD OF OPERATING THE SAME' [patent_app_type] => utility [patent_app_number] => 12/647725 [patent_app_country] => US [patent_app_date] => 2009-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6437 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0214/20100214849.pdf [firstpage_image] =>[orig_patent_app_number] => 12647725 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/647725
Page buffer circuit of nonvolatile memory device and method of operating the same Dec 27, 2009 Issued
Array ( [id] => 6508211 [patent_doc_number] => 20100202196 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-08-12 [patent_title] => 'METHOD OF READING NONVOLATILE MEMORY DEVICE AND NONVOLATILE MEMORY DEVICE FOR IMPLEMENTING THE METHOD' [patent_app_type] => utility [patent_app_number] => 12/647655 [patent_app_country] => US [patent_app_date] => 2009-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3644 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0202/20100202196.pdf [firstpage_image] =>[orig_patent_app_number] => 12647655 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/647655
Method of reading nonvolatile memory device and nonvolatile memory device for implementing the method Dec 27, 2009 Issued
Array ( [id] => 8404571 [patent_doc_number] => 20120236630 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-09-20 [patent_title] => 'BYPASS CAPACITOR CIRCUIT AND METHOD OF PROVIDING A BYPASS CAPACITANCE FOR AN INTEGRATED CIRCUIT DIE' [patent_app_type] => utility [patent_app_number] => 13/509922 [patent_app_country] => US [patent_app_date] => 2009-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3667 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13509922 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/509922
Bypass capacitor circuit and method of providing a bypass capacitance for an integrated circuit die Nov 29, 2009 Issued
Array ( [id] => 6361153 [patent_doc_number] => 20100073996 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-03-25 [patent_title] => 'SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 12/625739 [patent_app_country] => US [patent_app_date] => 2009-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 11721 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0073/20100073996.pdf [firstpage_image] =>[orig_patent_app_number] => 12625739 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/625739
Semiconductor device Nov 24, 2009 Issued
Array ( [id] => 8376720 [patent_doc_number] => 08259520 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-09-04 [patent_title] => 'Columnar replacement of defective memory cells' [patent_app_type] => utility [patent_app_number] => 12/592330 [patent_app_country] => US [patent_app_date] => 2009-11-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 18 [patent_no_of_words] => 14219 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12592330 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/592330
Columnar replacement of defective memory cells Nov 22, 2009 Issued
Array ( [id] => 8307180 [patent_doc_number] => 08228727 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-07-24 [patent_title] => 'Method for programming multi-level cell and memory apparatus' [patent_app_type] => utility [patent_app_number] => 12/623110 [patent_app_country] => US [patent_app_date] => 2009-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 2821 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12623110 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/623110
Method for programming multi-level cell and memory apparatus Nov 19, 2009 Issued
Array ( [id] => 8191914 [patent_doc_number] => 08184488 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-05-22 [patent_title] => 'Systems and methods for controlling integrated circuit operation with below ground pin voltage' [patent_app_type] => utility [patent_app_number] => 12/592240 [patent_app_country] => US [patent_app_date] => 2009-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 4663 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/184/08184488.pdf [firstpage_image] =>[orig_patent_app_number] => 12592240 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/592240
Systems and methods for controlling integrated circuit operation with below ground pin voltage Nov 19, 2009 Issued
Array ( [id] => 6564573 [patent_doc_number] => 20100128522 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-05-27 [patent_title] => 'Flash memory device and programming/erasing method of the same' [patent_app_type] => utility [patent_app_number] => 12/591428 [patent_app_country] => US [patent_app_date] => 2009-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5497 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0128/20100128522.pdf [firstpage_image] =>[orig_patent_app_number] => 12591428 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/591428
Flash memory device and programming/erasing method of the same Nov 18, 2009 Issued
Array ( [id] => 6530092 [patent_doc_number] => 20100124094 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-05-20 [patent_title] => 'DATA HOLDING DEVICE' [patent_app_type] => utility [patent_app_number] => 12/621812 [patent_app_country] => US [patent_app_date] => 2009-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 29 [patent_no_of_words] => 19532 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0124/20100124094.pdf [firstpage_image] =>[orig_patent_app_number] => 12621812 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/621812
Data holding device Nov 18, 2009 Issued
Array ( [id] => 8258799 [patent_doc_number] => 08208304 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-06-26 [patent_title] => 'Storage at M bits/cell density in N bits/cell analog memory cell devices, M>N' [patent_app_type] => utility [patent_app_number] => 12/618732 [patent_app_country] => US [patent_app_date] => 2009-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 9848 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12618732 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/618732
Storage at M bits/cell density in N bits/cell analog memory cell devices, M>N Nov 14, 2009 Issued
Array ( [id] => 7777299 [patent_doc_number] => 08120979 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-02-21 [patent_title] => 'Semiconductor memory devices having hierarchical bit-line structures' [patent_app_type] => utility [patent_app_number] => 12/591254 [patent_app_country] => US [patent_app_date] => 2009-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 8115 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/120/08120979.pdf [firstpage_image] =>[orig_patent_app_number] => 12591254 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/591254
Semiconductor memory devices having hierarchical bit-line structures Nov 12, 2009 Issued
Array ( [id] => 6276761 [patent_doc_number] => 20100118631 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-05-13 [patent_title] => 'Semiconductor memory devices with mismatch cells' [patent_app_type] => utility [patent_app_number] => 12/591196 [patent_app_country] => US [patent_app_date] => 2009-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7271 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0118/20100118631.pdf [firstpage_image] =>[orig_patent_app_number] => 12591196 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/591196
Semiconductor memory devices with mismatch cells Nov 11, 2009 Issued
Array ( [id] => 6276705 [patent_doc_number] => 20100118616 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-05-13 [patent_title] => 'Semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 12/591176 [patent_app_country] => US [patent_app_date] => 2009-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7733 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0118/20100118616.pdf [firstpage_image] =>[orig_patent_app_number] => 12591176 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/591176
Semiconductor memory device Nov 11, 2009 Issued
Array ( [id] => 6577769 [patent_doc_number] => 20100061155 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-03-11 [patent_title] => 'MEMORY ARRAY SEGMENTATION AND METHODS' [patent_app_type] => utility [patent_app_number] => 12/614750 [patent_app_country] => US [patent_app_date] => 2009-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4913 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0061/20100061155.pdf [firstpage_image] =>[orig_patent_app_number] => 12614750 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/614750
Memory array segmentation and methods Nov 8, 2009 Issued
Array ( [id] => 6589190 [patent_doc_number] => 20100097850 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-04-22 [patent_title] => 'APPARATUS AND SYSTEMS USING PHASE CHANGE MEMORIES' [patent_app_type] => utility [patent_app_number] => 12/611606 [patent_app_country] => US [patent_app_date] => 2009-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 8805 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0097/20100097850.pdf [firstpage_image] =>[orig_patent_app_number] => 12611606 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/611606
Apparatus and systems using phase change memories Nov 2, 2009 Issued
Array ( [id] => 6286104 [patent_doc_number] => 20100157644 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-06-24 [patent_title] => 'Configurable memory interface to provide serial and parallel access to memories' [patent_app_type] => utility [patent_app_number] => 12/587841 [patent_app_country] => US [patent_app_date] => 2009-10-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 13692 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0157/20100157644.pdf [firstpage_image] =>[orig_patent_app_number] => 12587841 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/587841
Configurable memory interface to provide serial and parallel access to memories Oct 12, 2009 Abandoned
Array ( [id] => 8154822 [patent_doc_number] => 08169835 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-05-01 [patent_title] => 'Charge trapping memory cell having bandgap engineered tunneling structure with oxynitride isolation layer' [patent_app_type] => utility [patent_app_number] => 12/568272 [patent_app_country] => US [patent_app_date] => 2009-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 24 [patent_no_of_words] => 9176 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/169/08169835.pdf [firstpage_image] =>[orig_patent_app_number] => 12568272 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/568272
Charge trapping memory cell having bandgap engineered tunneling structure with oxynitride isolation layer Sep 27, 2009 Issued
Array ( [id] => 8147962 [patent_doc_number] => 08164970 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-04-24 [patent_title] => 'Third dimensional memory with compress engine' [patent_app_type] => utility [patent_app_number] => 12/586478 [patent_app_country] => US [patent_app_date] => 2009-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 18 [patent_no_of_words] => 13148 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/164/08164970.pdf [firstpage_image] =>[orig_patent_app_number] => 12586478 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/586478
Third dimensional memory with compress engine Sep 21, 2009 Issued
Array ( [id] => 4630565 [patent_doc_number] => 08009470 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-08-30 [patent_title] => 'Nonvolatile semiconductor memory' [patent_app_type] => utility [patent_app_number] => 12/563296 [patent_app_country] => US [patent_app_date] => 2009-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 22 [patent_no_of_words] => 12076 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/009/08009470.pdf [firstpage_image] =>[orig_patent_app_number] => 12563296 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/563296
Nonvolatile semiconductor memory Sep 20, 2009 Issued
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