Search

David Lam

Examiner (ID: 14034, Phone: (571)272-1782 , Office: P/2825 )

Most Active Art Unit
2827
Art Unit(s)
2825, 2827, 2818
Total Applications
2102
Issued Applications
2016
Pending Applications
28
Abandoned Applications
60

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 5317593 [patent_doc_number] => 20090282191 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-11-12 [patent_title] => 'Operating Method for a Memory Subsystem and Devices for Executing the Operating Method' [patent_app_type] => utility [patent_app_number] => 12/463314 [patent_app_country] => US [patent_app_date] => 2009-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5686 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0282/20090282191.pdf [firstpage_image] =>[orig_patent_app_number] => 12463314 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/463314
Operating method for a memory subsystem and devices for executing the operating method May 7, 2009 Issued
Array ( [id] => 6280842 [patent_doc_number] => 20100257321 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-10-07 [patent_title] => 'PRIORITIZATION OF DIRECTORY SCANS IN CACHE' [patent_app_type] => utility [patent_app_number] => 12/418777 [patent_app_country] => US [patent_app_date] => 2009-04-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3343 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0257/20100257321.pdf [firstpage_image] =>[orig_patent_app_number] => 12418777 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/418777
Prioritization of directory scans in cache Apr 5, 2009 Issued
Array ( [id] => 6280851 [patent_doc_number] => 20100257326 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-10-07 [patent_title] => 'METHOD AND APPARATUS FOR LOGICAL VOLUME MANAGEMENT FOR VIRTUAL MACHINE ENVIRONMENT' [patent_app_type] => utility [patent_app_number] => 12/418765 [patent_app_country] => US [patent_app_date] => 2009-04-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 31 [patent_no_of_words] => 6544 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0257/20100257326.pdf [firstpage_image] =>[orig_patent_app_number] => 12418765 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/418765
Method and apparatus for logical volume management for virtual machine environment Apr 5, 2009 Issued
Array ( [id] => 5354063 [patent_doc_number] => 20090185407 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-07-23 [patent_title] => 'Semiconductor Memory Device Having Transistors of Stacked Structure' [patent_app_type] => utility [patent_app_number] => 12/408932 [patent_app_country] => US [patent_app_date] => 2009-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 67 [patent_figures_cnt] => 67 [patent_no_of_words] => 23871 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0185/20090185407.pdf [firstpage_image] =>[orig_patent_app_number] => 12408932 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/408932
Semiconductor memory devices having vertically-stacked transistors therein Mar 22, 2009 Issued
Array ( [id] => 5408710 [patent_doc_number] => 20090122608 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-05-14 [patent_title] => 'MEMORY VOLTAGE CYCLE ADJUSTMENT' [patent_app_type] => utility [patent_app_number] => 12/354975 [patent_app_country] => US [patent_app_date] => 2009-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7836 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0122/20090122608.pdf [firstpage_image] =>[orig_patent_app_number] => 12354975 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/354975
Memory voltage cycle adjustment Jan 15, 2009 Issued
Array ( [id] => 5408725 [patent_doc_number] => 20090122623 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-05-14 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE AND DRIVING METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 12/354158 [patent_app_country] => US [patent_app_date] => 2009-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2074 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0122/20090122623.pdf [firstpage_image] =>[orig_patent_app_number] => 12354158 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/354158
Semiconductor memory device and driving method thereof Jan 14, 2009 Issued
Array ( [id] => 6421532 [patent_doc_number] => 20100142295 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-06-10 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE AND DRIVING METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 12/345030 [patent_app_country] => US [patent_app_date] => 2008-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5501 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0142/20100142295.pdf [firstpage_image] =>[orig_patent_app_number] => 12345030 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/345030
Semiconductor memory device and driving method thereof Dec 28, 2008 Issued
Array ( [id] => 6403779 [patent_doc_number] => 20100165753 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-07-01 [patent_title] => 'METHOD AND APPARATUS FOR REDUCING LEAKAGE IN BIT LINES OF A MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 12/345442 [patent_app_country] => US [patent_app_date] => 2008-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6023 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0165/20100165753.pdf [firstpage_image] =>[orig_patent_app_number] => 12345442 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/345442
Method and apparatus for reducing leakage in bit lines of a memory device Dec 28, 2008 Issued
Array ( [id] => 5366212 [patent_doc_number] => 20090303771 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-12-10 [patent_title] => 'RADIO FREQUENCY IDENTIFICATION DEVICE INITIALIZING A MEMORY USING AN OFFSET VOLTAGE' [patent_app_type] => utility [patent_app_number] => 12/344638 [patent_app_country] => US [patent_app_date] => 2008-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 5410 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0303/20090303771.pdf [firstpage_image] =>[orig_patent_app_number] => 12344638 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/344638
Radio frequency identification device initializing a memory using an offset voltage Dec 28, 2008 Issued
Array ( [id] => 4565343 [patent_doc_number] => 07821867 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-10-26 [patent_title] => 'Semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 12/344654 [patent_app_country] => US [patent_app_date] => 2008-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 10049 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/821/07821867.pdf [firstpage_image] =>[orig_patent_app_number] => 12344654 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/344654
Semiconductor memory device Dec 28, 2008 Issued
Array ( [id] => 4605566 [patent_doc_number] => 07986549 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-07-26 [patent_title] => 'Apparatus and method for refreshing or toggling a phase-change memory cell' [patent_app_type] => utility [patent_app_number] => 12/345462 [patent_app_country] => US [patent_app_date] => 2008-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 5173 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/986/07986549.pdf [firstpage_image] =>[orig_patent_app_number] => 12345462 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/345462
Apparatus and method for refreshing or toggling a phase-change memory cell Dec 28, 2008 Issued
Array ( [id] => 5396440 [patent_doc_number] => 20090316503 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-12-24 [patent_title] => 'CLOCK DRIVER DEVICE AND SEMICONDUCTOR MEMORY APPARATUS HAVING THE SAME' [patent_app_type] => utility [patent_app_number] => 12/345120 [patent_app_country] => US [patent_app_date] => 2008-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4769 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0316/20090316503.pdf [firstpage_image] =>[orig_patent_app_number] => 12345120 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/345120
Clock driver device and semiconductor memory apparatus having the same Dec 28, 2008 Issued
Array ( [id] => 4480840 [patent_doc_number] => 07869270 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-01-11 [patent_title] => 'Set algorithm for phase change memory cell' [patent_app_type] => utility [patent_app_number] => 12/345384 [patent_app_country] => US [patent_app_date] => 2008-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 21 [patent_no_of_words] => 7410 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/869/07869270.pdf [firstpage_image] =>[orig_patent_app_number] => 12345384 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/345384
Set algorithm for phase change memory cell Dec 28, 2008 Issued
Array ( [id] => 6411830 [patent_doc_number] => 20100149859 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-06-17 [patent_title] => 'PHASE-CHANGE MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 12/345396 [patent_app_country] => US [patent_app_date] => 2008-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5521 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0149/20100149859.pdf [firstpage_image] =>[orig_patent_app_number] => 12345396 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/345396
Phase-change memory device Dec 28, 2008 Issued
Array ( [id] => 4492351 [patent_doc_number] => 07885101 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-02-08 [patent_title] => 'Method for low-stress multilevel reading of phase change memory cells and multilevel phase change memory' [patent_app_type] => utility [patent_app_number] => 12/345398 [patent_app_country] => US [patent_app_date] => 2008-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 16 [patent_no_of_words] => 4634 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/885/07885101.pdf [firstpage_image] =>[orig_patent_app_number] => 12345398 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/345398
Method for low-stress multilevel reading of phase change memory cells and multilevel phase change memory Dec 28, 2008 Issued
Array ( [id] => 6517876 [patent_doc_number] => 20100014367 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-01-21 [patent_title] => 'MEMORY REPAIR CIRCUIT AND REPAIRABLE PSEUDO-DUAL PORT STATIC RANDOM ACCESS MEMORY' [patent_app_type] => utility [patent_app_number] => 12/344884 [patent_app_country] => US [patent_app_date] => 2008-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5620 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0014/20100014367.pdf [firstpage_image] =>[orig_patent_app_number] => 12344884 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/344884
Memory repair circuit and repairable pseudo-dual port static random access memory Dec 28, 2008 Issued
Array ( [id] => 6403394 [patent_doc_number] => 20100165690 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-07-01 [patent_title] => 'SEGMENTED TERNARY CONTENT ADDRESSABLE MEMORY SEARCH ARCHITECTURE' [patent_app_type] => utility [patent_app_number] => 12/344294 [patent_app_country] => US [patent_app_date] => 2008-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4319 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0165/20100165690.pdf [firstpage_image] =>[orig_patent_app_number] => 12344294 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/344294
Segmented ternary content addressable memory search architecture Dec 25, 2008 Issued
Array ( [id] => 6577738 [patent_doc_number] => 20100061153 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-03-11 [patent_title] => 'Refresh Method for a Non-volatile Memory' [patent_app_type] => utility [patent_app_number] => 12/344288 [patent_app_country] => US [patent_app_date] => 2008-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1790 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0061/20100061153.pdf [firstpage_image] =>[orig_patent_app_number] => 12344288 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/344288
Refresh Method for a Non-volatile Memory Dec 25, 2008 Abandoned
Array ( [id] => 5433974 [patent_doc_number] => 20090168560 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-07-02 [patent_title] => 'CIRCUIT AND METHOD FOR CONTROLLING LOCAL DATA LINE IN SEMICONDUCTOR MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 12/344062 [patent_app_country] => US [patent_app_date] => 2008-12-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2543 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0168/20090168560.pdf [firstpage_image] =>[orig_patent_app_number] => 12344062 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/344062
Circuit and method for controlling local data line in semiconductor memory device Dec 23, 2008 Issued
Array ( [id] => 4445141 [patent_doc_number] => 07929333 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-04-19 [patent_title] => 'Semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 12/343996 [patent_app_country] => US [patent_app_date] => 2008-12-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 13 [patent_no_of_words] => 4748 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 230 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/929/07929333.pdf [firstpage_image] =>[orig_patent_app_number] => 12343996 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/343996
Semiconductor memory device Dec 23, 2008 Issued
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