
David Lam
Examiner (ID: 14034, Phone: (571)272-1782 , Office: P/2825 )
| Most Active Art Unit | 2827 |
| Art Unit(s) | 2825, 2827, 2818 |
| Total Applications | 2102 |
| Issued Applications | 2016 |
| Pending Applications | 28 |
| Abandoned Applications | 60 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 5445301
[patent_doc_number] => 20090046527
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-02-19
[patent_title] => 'AUTO PRECHARGE CIRCUIT SHARING A WRITE AUTO PRECHARGE SIGNAL GENERATING UNIT'
[patent_app_type] => utility
[patent_app_number] => 12/137040
[patent_app_country] => US
[patent_app_date] => 2008-06-11
[patent_effective_date] => 0000-00-00
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[pdf_file] => publications/A1/0046/20090046527.pdf
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/137040 | Auto precharge circuit sharing a write auto precharge signal generating unit | Jun 10, 2008 | Issued |
Array
(
[id] => 6613
[patent_doc_number] => 07817479
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[patent_kind] => B2
[patent_issue_date] => 2010-10-19
[patent_title] => 'Nonvolatile memory device using a variable resistive element and associated operating method'
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Array
(
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[patent_doc_number] => 20080293199
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[patent_issue_date] => 2008-11-27
[patent_title] => 'SINGLE-POLY NON-VOLATILE MEMORY DEVICE AND ITS OPERATION METHOD'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/125912 | Single-poly non-volatile memory device and its operation method | May 21, 2008 | Issued |
Array
(
[id] => 170843
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[patent_issue_date] => 2010-02-23
[patent_title] => 'Memory system including a resistance variable memory device'
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Array
(
[id] => 286555
[patent_doc_number] => 07551485
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[patent_title] => 'Semiconductor memory device'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/106892 | Semiconductor memory device | Apr 20, 2008 | Issued |
Array
(
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[patent_title] => 'Memory repair system and method'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/082760 | Memory repair system and method | Apr 13, 2008 | Issued |
Array
(
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[patent_title] => 'Adjustable width strobe interface'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/532914 | Adjustable width strobe interface | Mar 26, 2008 | Issued |
Array
(
[id] => 364843
[patent_doc_number] => 07483304
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[patent_issue_date] => 2009-01-27
[patent_title] => 'Semiconductor memory device capable of setting a negative threshold voltage'
[patent_app_type] => utility
[patent_app_number] => 12/055074
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[pdf_file] => patents/07/483/07483304.pdf
[firstpage_image] =>[orig_patent_app_number] => 12055074
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/055074 | Semiconductor memory device capable of setting a negative threshold voltage | Mar 24, 2008 | Issued |
Array
(
[id] => 4725646
[patent_doc_number] => 20080205187
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[patent_kind] => A1
[patent_issue_date] => 2008-08-28
[patent_title] => 'DATA FLOW CONTROL IN MULTIPLE INDEPENDENT PORT'
[patent_app_type] => utility
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/034686 | Data flow control in multiple independent port | Feb 20, 2008 | Issued |
Array
(
[id] => 4730330
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[patent_issue_date] => 2008-08-28
[patent_title] => 'OVER-SAMPLING READ OPERATION FOR A FLASH MEMORY DEVICE'
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[patent_app_number] => 12/034872
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/034872 | Over-sampling read operation for a flash memory device | Feb 20, 2008 | Issued |
Array
(
[id] => 578425
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[patent_title] => 'Low-voltage reading device in particular for MRAM memory'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/033795 | Low-voltage reading device in particular for MRAM memory | Feb 18, 2008 | Issued |
Array
(
[id] => 5478799
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[patent_title] => 'Method and Circuit for Implementing Enhanced Efuse Sense Circuit'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/029010 | Method and circuit for implementing enhanced eFuse sense circuit | Feb 10, 2008 | Issued |
Array
(
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[patent_title] => 'PROGRAMMABLE SRAM SOURCE BIAS SCHEME FOR USE WITH SWITCHABLE SRAM POWER SUPPLY SETS OF VOLTAGES'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/029366 | Programmable SRAM source bias scheme for use with switchable SRAM power supply sets of voltages | Feb 10, 2008 | Issued |
Array
(
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[patent_title] => 'Auto-precharge control circuit in semiconductor memory and method thereof'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/068280 | Auto-precharge control circuit in semiconductor memory and method thereof | Feb 4, 2008 | Abandoned |
Array
(
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/068273 | Power voltage supplier of semiconductor memory device | Feb 4, 2008 | Issued |
Array
(
[id] => 4625576
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Array
(
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Array
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Array
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Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/966631 | Method and apparatus for reduction of bit-line disturb and soft-erase in a trapped-charge memory | Dec 27, 2007 | Issued |