Search

David Lam

Examiner (ID: 14034, Phone: (571)272-1782 , Office: P/2825 )

Most Active Art Unit
2827
Art Unit(s)
2825, 2827, 2818
Total Applications
2102
Issued Applications
2016
Pending Applications
28
Abandoned Applications
60

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 237044 [patent_doc_number] => 07596027 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-09-29 [patent_title] => 'Semiconductor storage device having page copying function' [patent_app_type] => utility [patent_app_number] => 12/004546 [patent_app_country] => US [patent_app_date] => 2007-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 4897 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/596/07596027.pdf [firstpage_image] =>[orig_patent_app_number] => 12004546 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/004546
Semiconductor storage device having page copying function Dec 20, 2007 Issued
Array ( [id] => 7516637 [patent_doc_number] => 08040717 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-10-18 [patent_title] => 'SRAM cell and SRAM device' [patent_app_type] => utility [patent_app_number] => 12/521408 [patent_app_country] => US [patent_app_date] => 2007-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 4768 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 31 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/040/08040717.pdf [firstpage_image] =>[orig_patent_app_number] => 12521408 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/521408
SRAM cell and SRAM device Dec 19, 2007 Issued
Array ( [id] => 4914312 [patent_doc_number] => 20080094912 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-04-24 [patent_title] => 'SELECTIVE SLOW PROGRAMMING CONVERGENCE IN A FLASH MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 11/958620 [patent_app_country] => US [patent_app_date] => 2007-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3740 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0094/20080094912.pdf [firstpage_image] =>[orig_patent_app_number] => 11958620 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/958620
SELECTIVE SLOW PROGRAMMING CONVERGENCE IN A FLASH MEMORY DEVICE Dec 17, 2007 Abandoned
Array ( [id] => 46552 [patent_doc_number] => 07778095 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-08-17 [patent_title] => 'Semiconductor memory device and method for driving the same' [patent_app_type] => utility [patent_app_number] => 12/000698 [patent_app_country] => US [patent_app_date] => 2007-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3167 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/778/07778095.pdf [firstpage_image] =>[orig_patent_app_number] => 12000698 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/000698
Semiconductor memory device and method for driving the same Dec 16, 2007 Issued
Array ( [id] => 55596 [patent_doc_number] => 07773436 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-08-10 [patent_title] => 'Semiconductor device' [patent_app_type] => utility [patent_app_number] => 12/000592 [patent_app_country] => US [patent_app_date] => 2007-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 29 [patent_no_of_words] => 16511 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/773/07773436.pdf [firstpage_image] =>[orig_patent_app_number] => 12000592 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/000592
Semiconductor device Dec 13, 2007 Issued
Array ( [id] => 104619 [patent_doc_number] => 07729185 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-06-01 [patent_title] => 'Apparatus and method for detection of address decoder open faults' [patent_app_type] => utility [patent_app_number] => 12/000600 [patent_app_country] => US [patent_app_date] => 2007-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 8529 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/729/07729185.pdf [firstpage_image] =>[orig_patent_app_number] => 12000600 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/000600
Apparatus and method for detection of address decoder open faults Dec 13, 2007 Issued
Array ( [id] => 164731 [patent_doc_number] => 07672188 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-03-02 [patent_title] => 'System for blocking multiple memory read port activation' [patent_app_type] => utility [patent_app_number] => 11/954791 [patent_app_country] => US [patent_app_date] => 2007-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2771 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/672/07672188.pdf [firstpage_image] =>[orig_patent_app_number] => 11954791 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/954791
System for blocking multiple memory read port activation Dec 11, 2007 Issued
Array ( [id] => 124291 [patent_doc_number] => 07710800 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-05-04 [patent_title] => 'Managing redundant memory in a voltage island' [patent_app_type] => utility [patent_app_number] => 11/954479 [patent_app_country] => US [patent_app_date] => 2007-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5026 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 47 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/710/07710800.pdf [firstpage_image] =>[orig_patent_app_number] => 11954479 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/954479
Managing redundant memory in a voltage island Dec 11, 2007 Issued
Array ( [id] => 164722 [patent_doc_number] => 07672183 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-03-02 [patent_title] => 'Semiconductor memory device with two-stage input buffer' [patent_app_type] => utility [patent_app_number] => 12/000230 [patent_app_country] => US [patent_app_date] => 2007-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 2767 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/672/07672183.pdf [firstpage_image] =>[orig_patent_app_number] => 12000230 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/000230
Semiconductor memory device with two-stage input buffer Dec 10, 2007 Issued
Array ( [id] => 4548881 [patent_doc_number] => 07876632 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-01-25 [patent_title] => 'Semiconductor memory device and method for repairing the same' [patent_app_type] => utility [patent_app_number] => 12/000208 [patent_app_country] => US [patent_app_date] => 2007-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4077 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/876/07876632.pdf [firstpage_image] =>[orig_patent_app_number] => 12000208 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/000208
Semiconductor memory device and method for repairing the same Dec 10, 2007 Issued
Array ( [id] => 84236 [patent_doc_number] => 07746705 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-06-29 [patent_title] => 'Selective application of word line bias to minimize fringe effects in electromagnetic fields during erase of nonvolatile memory' [patent_app_type] => utility [patent_app_number] => 11/953689 [patent_app_country] => US [patent_app_date] => 2007-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 15 [patent_no_of_words] => 17700 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 270 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/746/07746705.pdf [firstpage_image] =>[orig_patent_app_number] => 11953689 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/953689
Selective application of word line bias to minimize fringe effects in electromagnetic fields during erase of nonvolatile memory Dec 9, 2007 Issued
Array ( [id] => 4584597 [patent_doc_number] => 07826275 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-11-02 [patent_title] => 'Memory circuit with high reading speed and low switching noise' [patent_app_type] => utility [patent_app_number] => 11/953161 [patent_app_country] => US [patent_app_date] => 2007-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3279 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/826/07826275.pdf [firstpage_image] =>[orig_patent_app_number] => 11953161 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/953161
Memory circuit with high reading speed and low switching noise Dec 9, 2007 Issued
Array ( [id] => 240552 [patent_doc_number] => 07593274 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-09-22 [patent_title] => 'Semiconductor integrated circuit and relief method and test method of the same' [patent_app_type] => utility [patent_app_number] => 11/953623 [patent_app_country] => US [patent_app_date] => 2007-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 3592 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/593/07593274.pdf [firstpage_image] =>[orig_patent_app_number] => 11953623 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/953623
Semiconductor integrated circuit and relief method and test method of the same Dec 9, 2007 Issued
Array ( [id] => 4865304 [patent_doc_number] => 20080144363 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-06-19 [patent_title] => 'METHOD OF TESTING PRAM DEVICE' [patent_app_type] => utility [patent_app_number] => 11/953146 [patent_app_country] => US [patent_app_date] => 2007-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3769 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0144/20080144363.pdf [firstpage_image] =>[orig_patent_app_number] => 11953146 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/953146
Method of testing PRAM device Dec 9, 2007 Issued
Array ( [id] => 5421150 [patent_doc_number] => 20090147605 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-06-11 [patent_title] => 'NOVEL HIGH PERFORMANCE, AREA EFFICIENT DIRECT BITLINE SENSING CIRCUIT' [patent_app_type] => utility [patent_app_number] => 11/953075 [patent_app_country] => US [patent_app_date] => 2007-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 8693 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0147/20090147605.pdf [firstpage_image] =>[orig_patent_app_number] => 11953075 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/953075
High performance, area efficient direct bitline sensing circuit Dec 9, 2007 Issued
Array ( [id] => 257363 [patent_doc_number] => 07577043 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-08-18 [patent_title] => 'Voltage regulator for semiconductor memory' [patent_app_type] => utility [patent_app_number] => 11/953077 [patent_app_country] => US [patent_app_date] => 2007-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3904 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/577/07577043.pdf [firstpage_image] =>[orig_patent_app_number] => 11953077 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/953077
Voltage regulator for semiconductor memory Dec 9, 2007 Issued
Array ( [id] => 244254 [patent_doc_number] => 07589992 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-09-15 [patent_title] => 'Semiconductor device having three dimensional structure' [patent_app_type] => utility [patent_app_number] => 11/953289 [patent_app_country] => US [patent_app_date] => 2007-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 56 [patent_figures_cnt] => 90 [patent_no_of_words] => 23873 [patent_no_of_claims] => 43 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/589/07589992.pdf [firstpage_image] =>[orig_patent_app_number] => 11953289 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/953289
Semiconductor device having three dimensional structure Dec 9, 2007 Issued
Array ( [id] => 4725578 [patent_doc_number] => 20080205119 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-08-28 [patent_title] => 'NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 11/953412 [patent_app_country] => US [patent_app_date] => 2007-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 7033 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0205/20080205119.pdf [firstpage_image] =>[orig_patent_app_number] => 11953412 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/953412
Non-volatile semiconductor memory device Dec 9, 2007 Issued
Array ( [id] => 229834 [patent_doc_number] => 07602651 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-10-13 [patent_title] => 'Semiconductor integrated circuit device' [patent_app_type] => utility [patent_app_number] => 11/953319 [patent_app_country] => US [patent_app_date] => 2007-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5907 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/602/07602651.pdf [firstpage_image] =>[orig_patent_app_number] => 11953319 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/953319
Semiconductor integrated circuit device Dec 9, 2007 Issued
Array ( [id] => 179010 [patent_doc_number] => 07656721 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-02-02 [patent_title] => 'Semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/952976 [patent_app_country] => US [patent_app_date] => 2007-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3007 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 245 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/656/07656721.pdf [firstpage_image] =>[orig_patent_app_number] => 11952976 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/952976
Semiconductor device Dec 6, 2007 Issued
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