
David Lam
Examiner (ID: 14034, Phone: (571)272-1782 , Office: P/2825 )
| Most Active Art Unit | 2827 |
| Art Unit(s) | 2825, 2827, 2818 |
| Total Applications | 2102 |
| Issued Applications | 2016 |
| Pending Applications | 28 |
| Abandoned Applications | 60 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 237044
[patent_doc_number] => 07596027
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-09-29
[patent_title] => 'Semiconductor storage device having page copying function'
[patent_app_type] => utility
[patent_app_number] => 12/004546
[patent_app_country] => US
[patent_app_date] => 2007-12-21
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[pdf_file] => patents/07/596/07596027.pdf
[firstpage_image] =>[orig_patent_app_number] => 12004546
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/004546 | Semiconductor storage device having page copying function | Dec 20, 2007 | Issued |
Array
(
[id] => 7516637
[patent_doc_number] => 08040717
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-10-18
[patent_title] => 'SRAM cell and SRAM device'
[patent_app_type] => utility
[patent_app_number] => 12/521408
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[pdf_file] => patents/08/040/08040717.pdf
[firstpage_image] =>[orig_patent_app_number] => 12521408
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/521408 | SRAM cell and SRAM device | Dec 19, 2007 | Issued |
Array
(
[id] => 4914312
[patent_doc_number] => 20080094912
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[patent_kind] => A1
[patent_issue_date] => 2008-04-24
[patent_title] => 'SELECTIVE SLOW PROGRAMMING CONVERGENCE IN A FLASH MEMORY DEVICE'
[patent_app_type] => utility
[patent_app_number] => 11/958620
[patent_app_country] => US
[patent_app_date] => 2007-12-18
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[pdf_file] => publications/A1/0094/20080094912.pdf
[firstpage_image] =>[orig_patent_app_number] => 11958620
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/958620 | SELECTIVE SLOW PROGRAMMING CONVERGENCE IN A FLASH MEMORY DEVICE | Dec 17, 2007 | Abandoned |
Array
(
[id] => 46552
[patent_doc_number] => 07778095
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-08-17
[patent_title] => 'Semiconductor memory device and method for driving the same'
[patent_app_type] => utility
[patent_app_number] => 12/000698
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[patent_app_date] => 2007-12-17
[patent_effective_date] => 0000-00-00
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/000698 | Semiconductor memory device and method for driving the same | Dec 16, 2007 | Issued |
Array
(
[id] => 55596
[patent_doc_number] => 07773436
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[patent_issue_date] => 2010-08-10
[patent_title] => 'Semiconductor device'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/000592 | Semiconductor device | Dec 13, 2007 | Issued |
Array
(
[id] => 104619
[patent_doc_number] => 07729185
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[patent_issue_date] => 2010-06-01
[patent_title] => 'Apparatus and method for detection of address decoder open faults'
[patent_app_type] => utility
[patent_app_number] => 12/000600
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[firstpage_image] =>[orig_patent_app_number] => 12000600
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/000600 | Apparatus and method for detection of address decoder open faults | Dec 13, 2007 | Issued |
Array
(
[id] => 164731
[patent_doc_number] => 07672188
[patent_country] => US
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[patent_issue_date] => 2010-03-02
[patent_title] => 'System for blocking multiple memory read port activation'
[patent_app_type] => utility
[patent_app_number] => 11/954791
[patent_app_country] => US
[patent_app_date] => 2007-12-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
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[pdf_file] => patents/07/672/07672188.pdf
[firstpage_image] =>[orig_patent_app_number] => 11954791
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/954791 | System for blocking multiple memory read port activation | Dec 11, 2007 | Issued |
Array
(
[id] => 124291
[patent_doc_number] => 07710800
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[patent_kind] => B2
[patent_issue_date] => 2010-05-04
[patent_title] => 'Managing redundant memory in a voltage island'
[patent_app_type] => utility
[patent_app_number] => 11/954479
[patent_app_country] => US
[patent_app_date] => 2007-12-12
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[pdf_file] => patents/07/710/07710800.pdf
[firstpage_image] =>[orig_patent_app_number] => 11954479
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/954479 | Managing redundant memory in a voltage island | Dec 11, 2007 | Issued |
Array
(
[id] => 164722
[patent_doc_number] => 07672183
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-03-02
[patent_title] => 'Semiconductor memory device with two-stage input buffer'
[patent_app_type] => utility
[patent_app_number] => 12/000230
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[pdf_file] => patents/07/672/07672183.pdf
[firstpage_image] =>[orig_patent_app_number] => 12000230
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/000230 | Semiconductor memory device with two-stage input buffer | Dec 10, 2007 | Issued |
Array
(
[id] => 4548881
[patent_doc_number] => 07876632
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[patent_issue_date] => 2011-01-25
[patent_title] => 'Semiconductor memory device and method for repairing the same'
[patent_app_type] => utility
[patent_app_number] => 12/000208
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[pdf_file] => patents/07/876/07876632.pdf
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/000208 | Semiconductor memory device and method for repairing the same | Dec 10, 2007 | Issued |
Array
(
[id] => 84236
[patent_doc_number] => 07746705
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[patent_issue_date] => 2010-06-29
[patent_title] => 'Selective application of word line bias to minimize fringe effects in electromagnetic fields during erase of nonvolatile memory'
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[patent_app_number] => 11/953689
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[pdf_file] => patents/07/746/07746705.pdf
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/953689 | Selective application of word line bias to minimize fringe effects in electromagnetic fields during erase of nonvolatile memory | Dec 9, 2007 | Issued |
Array
(
[id] => 4584597
[patent_doc_number] => 07826275
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[patent_title] => 'Memory circuit with high reading speed and low switching noise'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/953161 | Memory circuit with high reading speed and low switching noise | Dec 9, 2007 | Issued |
Array
(
[id] => 240552
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Array
(
[id] => 4865304
[patent_doc_number] => 20080144363
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[patent_title] => 'METHOD OF TESTING PRAM DEVICE'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/953146 | Method of testing PRAM device | Dec 9, 2007 | Issued |
Array
(
[id] => 5421150
[patent_doc_number] => 20090147605
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[patent_title] => 'NOVEL HIGH PERFORMANCE, AREA EFFICIENT DIRECT BITLINE SENSING CIRCUIT'
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Array
(
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/953077 | Voltage regulator for semiconductor memory | Dec 9, 2007 | Issued |
Array
(
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Array
(
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Array
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Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/952976 | Semiconductor device | Dec 6, 2007 | Issued |