Search

David Lam

Examiner (ID: 14034, Phone: (571)272-1782 , Office: P/2825 )

Most Active Art Unit
2827
Art Unit(s)
2825, 2827, 2818
Total Applications
2102
Issued Applications
2016
Pending Applications
28
Abandoned Applications
60

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4686851 [patent_doc_number] => 20080031032 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-02-07 [patent_title] => 'Method and apparatus processing variable resistance memory cell write operation' [patent_app_type] => utility [patent_app_number] => 11/905823 [patent_app_country] => US [patent_app_date] => 2007-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4548 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0031/20080031032.pdf [firstpage_image] =>[orig_patent_app_number] => 11905823 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/905823
Method and apparatus processing variable resistance memory cell write operation Oct 3, 2007 Issued
Array ( [id] => 4806867 [patent_doc_number] => 20080170445 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-07-17 [patent_title] => 'Semiconductor memory having function to determine semiconductor low current' [patent_app_type] => utility [patent_app_number] => 11/905646 [patent_app_country] => US [patent_app_date] => 2007-10-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 10357 [patent_no_of_claims] => 52 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0170/20080170445.pdf [firstpage_image] =>[orig_patent_app_number] => 11905646 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/905646
Semiconductor memory having function to determine semiconductor low current Oct 2, 2007 Issued
Array ( [id] => 198893 [patent_doc_number] => 07639539 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-12-29 [patent_title] => 'Method and apparatus for programming data of memory cells considering floating poly coupling' [patent_app_type] => utility [patent_app_number] => 11/905674 [patent_app_country] => US [patent_app_date] => 2007-10-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4100 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/639/07639539.pdf [firstpage_image] =>[orig_patent_app_number] => 11905674 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/905674
Method and apparatus for programming data of memory cells considering floating poly coupling Oct 2, 2007 Issued
Array ( [id] => 304602 [patent_doc_number] => 07535748 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-05-19 [patent_title] => 'Semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 11/905532 [patent_app_country] => US [patent_app_date] => 2007-10-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5053 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 220 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/535/07535748.pdf [firstpage_image] =>[orig_patent_app_number] => 11905532 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/905532
Semiconductor memory device Oct 1, 2007 Issued
Array ( [id] => 192012 [patent_doc_number] => 07643331 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-01-05 [patent_title] => 'Semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/866144 [patent_app_country] => US [patent_app_date] => 2007-10-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 11711 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/643/07643331.pdf [firstpage_image] =>[orig_patent_app_number] => 11866144 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/866144
Semiconductor device Oct 1, 2007 Issued
Array ( [id] => 4908406 [patent_doc_number] => 20080019172 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-01-24 [patent_title] => 'Gated Diode Nonvolatile Memory Cell Array' [patent_app_type] => utility [patent_app_number] => 11/865616 [patent_app_country] => US [patent_app_date] => 2007-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 8348 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0019/20080019172.pdf [firstpage_image] =>[orig_patent_app_number] => 11865616 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/865616
Gated diode nonvolatile memory cell array Sep 30, 2007 Issued
Array ( [id] => 4926214 [patent_doc_number] => 20080165577 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-07-10 [patent_title] => 'Semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/904978 [patent_app_country] => US [patent_app_date] => 2007-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 8465 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0165/20080165577.pdf [firstpage_image] =>[orig_patent_app_number] => 11904978 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/904978
Semiconductor device Sep 27, 2007 Abandoned
Array ( [id] => 221996 [patent_doc_number] => 07609543 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-10-27 [patent_title] => 'Method and implementation of stress test for MRAM' [patent_app_type] => utility [patent_app_number] => 11/904434 [patent_app_country] => US [patent_app_date] => 2007-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2684 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/609/07609543.pdf [firstpage_image] =>[orig_patent_app_number] => 11904434 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/904434
Method and implementation of stress test for MRAM Sep 26, 2007 Issued
Array ( [id] => 297088 [patent_doc_number] => 07542365 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-06-02 [patent_title] => 'Apparatus and method for accessing a synchronous serial memory having unknown address bit field size' [patent_app_type] => utility [patent_app_number] => 11/862856 [patent_app_country] => US [patent_app_date] => 2007-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6174 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/542/07542365.pdf [firstpage_image] =>[orig_patent_app_number] => 11862856 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/862856
Apparatus and method for accessing a synchronous serial memory having unknown address bit field size Sep 26, 2007 Issued
Array ( [id] => 5427246 [patent_doc_number] => 20090086556 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-04-02 [patent_title] => 'Methods and apparatuses for operating memory' [patent_app_type] => utility [patent_app_number] => 11/904490 [patent_app_country] => US [patent_app_date] => 2007-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5621 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0086/20090086556.pdf [firstpage_image] =>[orig_patent_app_number] => 11904490 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/904490
Methods and apparatuses for operating memory Sep 26, 2007 Abandoned
Array ( [id] => 36080 [patent_doc_number] => 07787291 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-08-31 [patent_title] => 'Programming a multilevel phase change memory cell' [patent_app_type] => utility [patent_app_number] => 11/904306 [patent_app_country] => US [patent_app_date] => 2007-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 25 [patent_no_of_words] => 5430 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/787/07787291.pdf [firstpage_image] =>[orig_patent_app_number] => 11904306 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/904306
Programming a multilevel phase change memory cell Sep 25, 2007 Issued
Array ( [id] => 4691966 [patent_doc_number] => 20080084736 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-04-10 [patent_title] => 'Multi-port phase change random access memory cell and multi-port phase change random access memory device including the same' [patent_app_type] => utility [patent_app_number] => 11/902704 [patent_app_country] => US [patent_app_date] => 2007-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3955 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0084/20080084736.pdf [firstpage_image] =>[orig_patent_app_number] => 11902704 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/902704
Multi-port phase change random access memory cell and multi-port phase change random access memory device including the same Sep 24, 2007 Issued
Array ( [id] => 125521 [patent_doc_number] => 07706180 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-04-27 [patent_title] => 'Method and apparatus for reduction of bit-line disturb and soft-erase in a trapped-charge memory' [patent_app_type] => utility [patent_app_number] => 11/904112 [patent_app_country] => US [patent_app_date] => 2007-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 6235 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/706/07706180.pdf [firstpage_image] =>[orig_patent_app_number] => 11904112 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/904112
Method and apparatus for reduction of bit-line disturb and soft-erase in a trapped-charge memory Sep 24, 2007 Issued
Array ( [id] => 5507042 [patent_doc_number] => 20090080249 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-03-26 [patent_title] => 'Non-volatile memory cell endurance using data encoding' [patent_app_type] => utility [patent_app_number] => 11/903764 [patent_app_country] => US [patent_app_date] => 2007-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 4228 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0080/20090080249.pdf [firstpage_image] =>[orig_patent_app_number] => 11903764 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/903764
Non-volatile memory cell endurance using data encoding Sep 23, 2007 Issued
Array ( [id] => 4942915 [patent_doc_number] => 20080080240 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-04-03 [patent_title] => 'Memory devices and memory systems having the same' [patent_app_type] => utility [patent_app_number] => 11/902424 [patent_app_country] => US [patent_app_date] => 2007-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5804 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0080/20080080240.pdf [firstpage_image] =>[orig_patent_app_number] => 11902424 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/902424
Memory devices and memory systems having the same Sep 20, 2007 Issued
Array ( [id] => 4942931 [patent_doc_number] => 20080080256 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-04-03 [patent_title] => 'Delay circuit for controlling a pre-charging time of bit lines of a memory cell array' [patent_app_type] => utility [patent_app_number] => 11/902220 [patent_app_country] => US [patent_app_date] => 2007-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6598 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0080/20080080256.pdf [firstpage_image] =>[orig_patent_app_number] => 11902220 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/902220
Delay circuit for controlling a pre-charging time of bit lines of a memory cell array Sep 19, 2007 Issued
Array ( [id] => 4937619 [patent_doc_number] => 20080074936 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-03-27 [patent_title] => 'Read operation of multi-port memory device' [patent_app_type] => utility [patent_app_number] => 11/903170 [patent_app_country] => US [patent_app_date] => 2007-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 10935 [patent_no_of_claims] => 62 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0074/20080074936.pdf [firstpage_image] =>[orig_patent_app_number] => 11903170 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/903170
Read operation of multi-port memory device Sep 19, 2007 Issued
Array ( [id] => 4796408 [patent_doc_number] => 20080007994 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-01-10 [patent_title] => 'Synthetic anti-ferromagnetic structure with non-magnetic spacer for MRAM applications' [patent_app_type] => utility [patent_app_number] => 11/901080 [patent_app_country] => US [patent_app_date] => 2007-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7141 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0007/20080007994.pdf [firstpage_image] =>[orig_patent_app_number] => 11901080 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/901080
Synthetic anti-ferromagnetic structure with non-magnetic spacer for MRAM applications Sep 13, 2007 Issued
Array ( [id] => 289864 [patent_doc_number] => 07548483 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-06-16 [patent_title] => 'Memory device and method having multiple address, data and command buses' [patent_app_type] => utility [patent_app_number] => 11/900296 [patent_app_country] => US [patent_app_date] => 2007-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3291 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/548/07548483.pdf [firstpage_image] =>[orig_patent_app_number] => 11900296 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/900296
Memory device and method having multiple address, data and command buses Sep 9, 2007 Issued
Array ( [id] => 4686887 [patent_doc_number] => 20080031068 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-02-07 [patent_title] => 'DYNAMIC MEMORY REFRESH CONFIGURATIONS AND LEAKAGE CONTROL METHODS' [patent_app_type] => utility [patent_app_number] => 11/779716 [patent_app_country] => US [patent_app_date] => 2007-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 6898 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0031/20080031068.pdf [firstpage_image] =>[orig_patent_app_number] => 11779716 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/779716
Dynamic memory refresh configurations and leakage control methods Jul 17, 2007 Issued
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