Search

David Lam

Examiner (ID: 9389, Phone: (571)272-1782 , Office: P/2825 )

Most Active Art Unit
2827
Art Unit(s)
2818, 2827, 2825
Total Applications
2102
Issued Applications
2016
Pending Applications
28
Abandoned Applications
60

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4680991 [patent_doc_number] => 20080247217 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-09 [patent_title] => 'Integrated circuit, memory cell array, memory module, method of operating an integrated circuit, and computing system' [patent_app_type] => utility [patent_app_number] => 11/732696 [patent_app_country] => US [patent_app_date] => 2007-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7721 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0247/20080247217.pdf [firstpage_image] =>[orig_patent_app_number] => 11732696 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/732696
Integrated circuit, memory cell array, memory module, method of operating an integrated circuit, and computing system Apr 3, 2007 Abandoned
Array ( [id] => 5209333 [patent_doc_number] => 20070247917 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-10-25 [patent_title] => 'Method for programming a memory device suitable to minimize floating gate coupling and memory device' [patent_app_type] => utility [patent_app_number] => 11/732486 [patent_app_country] => US [patent_app_date] => 2007-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8468 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0247/20070247917.pdf [firstpage_image] =>[orig_patent_app_number] => 11732486 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/732486
Method for programming a memory device suitable to minimize floating gate coupling and memory device Apr 1, 2007 Issued
Array ( [id] => 4717311 [patent_doc_number] => 20080239833 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-02 [patent_title] => 'Readout of multi-level storage cells' [patent_app_type] => utility [patent_app_number] => 11/731766 [patent_app_country] => US [patent_app_date] => 2007-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3095 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0239/20080239833.pdf [firstpage_image] =>[orig_patent_app_number] => 11731766 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/731766
Readout of multi-level storage cells Mar 29, 2007 Issued
Array ( [id] => 5111693 [patent_doc_number] => 20070195608 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-08-23 [patent_title] => 'Germanium-silicon-carbide floating gates in memories' [patent_app_type] => utility [patent_app_number] => 11/731255 [patent_app_country] => US [patent_app_date] => 2007-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4151 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0195/20070195608.pdf [firstpage_image] =>[orig_patent_app_number] => 11731255 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/731255
Germanium-silicon-carbide floating gates in memories Mar 29, 2007 Abandoned
Array ( [id] => 233775 [patent_doc_number] => 07599208 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-10-06 [patent_title] => 'Nonvolatile ferroelectric memory device and refresh method thereof' [patent_app_type] => utility [patent_app_number] => 11/717048 [patent_app_country] => US [patent_app_date] => 2007-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 29 [patent_no_of_words] => 7506 [patent_no_of_claims] => 64 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/599/07599208.pdf [firstpage_image] =>[orig_patent_app_number] => 11717048 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/717048
Nonvolatile ferroelectric memory device and refresh method thereof Mar 12, 2007 Issued
Array ( [id] => 4818330 [patent_doc_number] => 20080225589 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-09-18 [patent_title] => 'Memory page boosting method, device and system' [patent_app_type] => utility [patent_app_number] => 11/717550 [patent_app_country] => US [patent_app_date] => 2007-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 8214 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0225/20080225589.pdf [firstpage_image] =>[orig_patent_app_number] => 11717550 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/717550
Memory page boosting method, device and system Mar 11, 2007 Issued
Array ( [id] => 5090615 [patent_doc_number] => 20070230254 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-10-04 [patent_title] => 'Method for deleting data from NAND type nonvolatile memory' [patent_app_type] => utility [patent_app_number] => 11/716672 [patent_app_country] => US [patent_app_date] => 2007-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 32 [patent_no_of_words] => 21468 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0230/20070230254.pdf [firstpage_image] =>[orig_patent_app_number] => 11716672 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/716672
Method for deleting data from NAND type nonvolatile memory Mar 11, 2007 Issued
Array ( [id] => 5218560 [patent_doc_number] => 20070159871 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-07-12 [patent_title] => 'Semiconductor device with a non-erasable memory and/or a nonvolatile memory' [patent_app_type] => utility [patent_app_number] => 11/715918 [patent_app_country] => US [patent_app_date] => 2007-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 32 [patent_no_of_words] => 17110 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0159/20070159871.pdf [firstpage_image] =>[orig_patent_app_number] => 11715918 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/715918
Semiconductor device with a non-erasable memory and/or a nonvolatile memory Mar 8, 2007 Issued
Array ( [id] => 5257924 [patent_doc_number] => 20070211556 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-09-13 [patent_title] => 'Input latency control circuit, a semiconductor memory device including an input latency control circuit and method thereof' [patent_app_type] => utility [patent_app_number] => 11/715478 [patent_app_country] => US [patent_app_date] => 2007-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 15437 [patent_no_of_claims] => 49 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0211/20070211556.pdf [firstpage_image] =>[orig_patent_app_number] => 11715478 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/715478
Input latency control circuit, a semiconductor memory device including an input latency control circuit and method thereof Mar 7, 2007 Issued
Array ( [id] => 5090614 [patent_doc_number] => 20070230253 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-10-04 [patent_title] => 'Non-volatile semiconductor memory with page erase' [patent_app_type] => utility [patent_app_number] => 11/715838 [patent_app_country] => US [patent_app_date] => 2007-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 45 [patent_figures_cnt] => 45 [patent_no_of_words] => 14272 [patent_no_of_claims] => 60 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0230/20070230253.pdf [firstpage_image] =>[orig_patent_app_number] => 11715838 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/715838
Non-volatile semiconductor memory with page erase Mar 7, 2007 Issued
Array ( [id] => 323662 [patent_doc_number] => 07518903 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-04-14 [patent_title] => 'Semiconductor memory device and semiconductor integrated circuit system' [patent_app_type] => utility [patent_app_number] => 11/712480 [patent_app_country] => US [patent_app_date] => 2007-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 14 [patent_no_of_words] => 10375 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/518/07518903.pdf [firstpage_image] =>[orig_patent_app_number] => 11712480 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/712480
Semiconductor memory device and semiconductor integrated circuit system Feb 28, 2007 Issued
Array ( [id] => 879305 [patent_doc_number] => 07359274 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-04-15 [patent_title] => 'Semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 11/678632 [patent_app_country] => US [patent_app_date] => 2007-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 35 [patent_figures_cnt] => 45 [patent_no_of_words] => 34519 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 359 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/359/07359274.pdf [firstpage_image] =>[orig_patent_app_number] => 11678632 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/678632
Semiconductor memory device Feb 25, 2007 Issued
Array ( [id] => 6298548 [patent_doc_number] => 20100067310 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-03-18 [patent_title] => 'MOS TRANSISTOR WITH A SETTABLE THRESHOLD' [patent_app_type] => utility [patent_app_number] => 12/279056 [patent_app_country] => US [patent_app_date] => 2007-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2717 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0067/20100067310.pdf [firstpage_image] =>[orig_patent_app_number] => 12279056 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/279056
MOS transistor with a settable threshold Feb 13, 2007 Issued
Array ( [id] => 4976034 [patent_doc_number] => 20070217265 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-09-20 [patent_title] => 'Low-voltage reading device in particular for MRAM memory' [patent_app_type] => utility [patent_app_number] => 11/701247 [patent_app_country] => US [patent_app_date] => 2007-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5006 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0217/20070217265.pdf [firstpage_image] =>[orig_patent_app_number] => 11701247 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/701247
Low-voltage reading device in particular for MRAM memory Jan 31, 2007 Abandoned
Array ( [id] => 5078137 [patent_doc_number] => 20070121361 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-05-31 [patent_title] => 'Semiconductor Memory Device, Electronic Card and Electronic Device' [patent_app_type] => utility [patent_app_number] => 11/625180 [patent_app_country] => US [patent_app_date] => 2007-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 4941 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0121/20070121361.pdf [firstpage_image] =>[orig_patent_app_number] => 11625180 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/625180
Semiconductor Memory Device, Electronic Card and Electronic Device Jan 18, 2007 Abandoned
Array ( [id] => 798578 [patent_doc_number] => 07428171 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-09-23 [patent_title] => 'Non-volatile memory and method with improved sensing' [patent_app_type] => utility [patent_app_number] => 11/621750 [patent_app_country] => US [patent_app_date] => 2007-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 32 [patent_no_of_words] => 17282 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 20 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/428/07428171.pdf [firstpage_image] =>[orig_patent_app_number] => 11621750 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/621750
Non-volatile memory and method with improved sensing Jan 9, 2007 Issued
Array ( [id] => 4969887 [patent_doc_number] => 20070109889 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-05-17 [patent_title] => 'Non-Volatile Memory and Method With Reduced Source Line Bias Errors' [patent_app_type] => utility [patent_app_number] => 11/620946 [patent_app_country] => US [patent_app_date] => 2007-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 14070 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0109/20070109889.pdf [firstpage_image] =>[orig_patent_app_number] => 11620946 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/620946
Non-volatile memory and method with reduced source line bias errors Jan 7, 2007 Issued
Array ( [id] => 834790 [patent_doc_number] => 07397697 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-07-08 [patent_title] => 'Multi-bit-per-cell flash EEPROM memory with refresh' [patent_app_type] => utility [patent_app_number] => 11/620127 [patent_app_country] => US [patent_app_date] => 2007-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 7046 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/397/07397697.pdf [firstpage_image] =>[orig_patent_app_number] => 11620127 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/620127
Multi-bit-per-cell flash EEPROM memory with refresh Jan 4, 2007 Issued
Array ( [id] => 4750982 [patent_doc_number] => 20080159053 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-07-03 [patent_title] => 'REVERSIBLE POLARITY DECODER CIRCUIT' [patent_app_type] => utility [patent_app_number] => 11/618844 [patent_app_country] => US [patent_app_date] => 2006-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 16955 [patent_no_of_claims] => 43 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0159/20080159053.pdf [firstpage_image] =>[orig_patent_app_number] => 11618844 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/618844
Reversible polarity decoder circuit Dec 30, 2006 Issued
Array ( [id] => 4750981 [patent_doc_number] => 20080159052 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-07-03 [patent_title] => 'METHOD FOR USING A REVERSIBLE POLARITY DECODER CIRCUIT' [patent_app_type] => utility [patent_app_number] => 11/618843 [patent_app_country] => US [patent_app_date] => 2006-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 16874 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0159/20080159052.pdf [firstpage_image] =>[orig_patent_app_number] => 11618843 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/618843
Method for using a reversible polarity decoder circuit Dec 30, 2006 Issued
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