
David Lam
Examiner (ID: 9389, Phone: (571)272-1782 , Office: P/2825 )
| Most Active Art Unit | 2827 |
| Art Unit(s) | 2818, 2827, 2825 |
| Total Applications | 2102 |
| Issued Applications | 2016 |
| Pending Applications | 28 |
| Abandoned Applications | 60 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 4680991
[patent_doc_number] => 20080247217
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[patent_issue_date] => 2008-10-09
[patent_title] => 'Integrated circuit, memory cell array, memory module, method of operating an integrated circuit, and computing system'
[patent_app_type] => utility
[patent_app_number] => 11/732696
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/732696 | Integrated circuit, memory cell array, memory module, method of operating an integrated circuit, and computing system | Apr 3, 2007 | Abandoned |
Array
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[patent_title] => 'Method for programming a memory device suitable to minimize floating gate coupling and memory device'
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Array
(
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[patent_doc_number] => 20080239833
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[patent_issue_date] => 2008-10-02
[patent_title] => 'Readout of multi-level storage cells'
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Array
(
[id] => 5111693
[patent_doc_number] => 20070195608
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[patent_issue_date] => 2007-08-23
[patent_title] => 'Germanium-silicon-carbide floating gates in memories'
[patent_app_type] => utility
[patent_app_number] => 11/731255
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[patent_app_date] => 2007-03-30
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Array
(
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[patent_title] => 'Nonvolatile ferroelectric memory device and refresh method thereof'
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[patent_app_number] => 11/717048
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/717048 | Nonvolatile ferroelectric memory device and refresh method thereof | Mar 12, 2007 | Issued |
Array
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[patent_title] => 'Memory page boosting method, device and system'
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Array
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Array
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[patent_title] => 'Semiconductor device with a non-erasable memory and/or a nonvolatile memory'
[patent_app_type] => utility
[patent_app_number] => 11/715918
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/715918 | Semiconductor device with a non-erasable memory and/or a nonvolatile memory | Mar 8, 2007 | Issued |
Array
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[patent_title] => 'Input latency control circuit, a semiconductor memory device including an input latency control circuit and method thereof'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/715478 | Input latency control circuit, a semiconductor memory device including an input latency control circuit and method thereof | Mar 7, 2007 | Issued |
Array
(
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[patent_title] => 'Non-volatile semiconductor memory with page erase'
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[patent_app_number] => 11/715838
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Array
(
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[patent_title] => 'Semiconductor memory device and semiconductor integrated circuit system'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/712480 | Semiconductor memory device and semiconductor integrated circuit system | Feb 28, 2007 | Issued |
Array
(
[id] => 879305
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Array
(
[id] => 6298548
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[patent_title] => 'MOS TRANSISTOR WITH A SETTABLE THRESHOLD'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/279056 | MOS transistor with a settable threshold | Feb 13, 2007 | Issued |
Array
(
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Array
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Array
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Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/618843 | Method for using a reversible polarity decoder circuit | Dec 30, 2006 | Issued |