David Lam

Array ( [id] => 929161 [patent_doc_number] => 07315473 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-01-01 [patent_title] => 'Semiconductor storage device having page copying function' [patent_app_type] => utility [patent_app_number] => 11/582065 [patent_app_country] => US [patent_app_date] => 2006-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 4876 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 355 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/315/07315473.pdf [firstpage_image] =>[orig_patent_app_number] => 11582065 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5105613 [patent_doc_number] => 20070064488 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-03-22 [patent_title] => 'EEPROM and method of driving the same' [patent_app_type] => utility [patent_app_number] => 11/524300 [patent_app_country] => US [patent_app_date] => 2006-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2302 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0064/20070064488.pdf [firstpage_image] =>[orig_patent_app_number] => 11524300 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5170300 [patent_doc_number] => 20070070731 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-03-29 [patent_title] => 'Delay locked operation in semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 11/523704 [patent_app_country] => US [patent_app_date] => 2006-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6059 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0070/20070070731.pdf [firstpage_image] =>[orig_patent_app_number] => 11523704 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 808437 [patent_doc_number] => 07420844 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-09-02 [patent_title] => 'Non-volatile semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 11/523564 [patent_app_country] => US [patent_app_date] => 2006-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6010 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 284 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/420/07420844.pdf [firstpage_image] =>[orig_patent_app_number] => 11523564 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5105604 [patent_doc_number] => 20070064479 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-03-22 [patent_title] => 'Non-volatile semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 11/523550 [patent_app_country] => US [patent_app_date] => 2006-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7347 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0064/20070064479.pdf [firstpage_image] =>[orig_patent_app_number] => 11523550 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 349837 [patent_doc_number] => 07495960 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-02-24 [patent_title] => 'Program methods for split-gate memory' [patent_app_type] => utility [patent_app_number] => 11/524128 [patent_app_country] => US [patent_app_date] => 2006-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 3178 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/495/07495960.pdf [firstpage_image] =>[orig_patent_app_number] => 11524128 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5009540 [patent_doc_number] => 20070280018 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-12-06 [patent_title] => 'Semiconductor memory device, a local precharge circuit and method thereof' [patent_app_type] => utility [patent_app_number] => 11/523052 [patent_app_country] => US [patent_app_date] => 2006-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4746 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0280/20070280018.pdf [firstpage_image] =>[orig_patent_app_number] => 11523052 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 186831 [patent_doc_number] => 07649795 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-01-19 [patent_title] => 'Memory with flexible serial interfaces and method for accessing memory thereof' [patent_app_type] => utility [patent_app_number] => 11/524235 [patent_app_country] => US [patent_app_date] => 2006-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5424 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/649/07649795.pdf [firstpage_image] =>[orig_patent_app_number] => 11524235 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 338979 [patent_doc_number] => 07505324 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-03-17 [patent_title] => 'Semiconductor memory device with a stacked gate including a floating gate and a control gate' [patent_app_type] => utility [patent_app_number] => 11/533051 [patent_app_country] => US [patent_app_date] => 2006-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 21 [patent_no_of_words] => 13906 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/505/07505324.pdf [firstpage_image] =>[orig_patent_app_number] => 11533051 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5218578 [patent_doc_number] => 20070159889 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-07-12 [patent_title] => 'Programming method for flash memory capable of compensating reduction of read margin between states due to hot temperature stress' [patent_app_type] => utility [patent_app_number] => 11/522406 [patent_app_country] => US [patent_app_date] => 2006-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4354 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0159/20070159889.pdf [firstpage_image] =>[orig_patent_app_number] => 11522406 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5105590 [patent_doc_number] => 20070064465 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-03-22 [patent_title] => 'ROM storing information by using pair of memory cells' [patent_app_type] => utility [patent_app_number] => 11/519232 [patent_app_country] => US [patent_app_date] => 2006-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4361 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0064/20070064465.pdf [firstpage_image] =>[orig_patent_app_number] => 11519232 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7600845 [patent_doc_number] => 07385864 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-06-10 [patent_title] => 'SRAM static noise margin test structure suitable for on chip parametric measurements' [patent_app_type] => utility [patent_app_number] => 11/519312 [patent_app_country] => US [patent_app_date] => 2006-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 19 [patent_no_of_words] => 10310 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/385/07385864.pdf [firstpage_image] =>[orig_patent_app_number] => 11519312 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 897777 [patent_doc_number] => 07342821 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-03-11 [patent_title] => 'Hot-carrier-based nonvolatile memory utilizing differing transistor structures' [patent_app_type] => utility [patent_app_number] => 11/518066 [patent_app_country] => US [patent_app_date] => 2006-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 46 [patent_no_of_words] => 8799 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 240 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/342/07342821.pdf [firstpage_image] =>[orig_patent_app_number] => 11518066 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 866842 [patent_doc_number] => 07369425 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-05-06 [patent_title] => 'Method and system for DRAM sensing' [patent_app_type] => utility [patent_app_number] => 11/517674 [patent_app_country] => US [patent_app_date] => 2006-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 2461 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/369/07369425.pdf [firstpage_image] =>[orig_patent_app_number] => 11517674 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 838499 [patent_doc_number] => 07394714 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-07-01 [patent_title] => 'Circuit implementation of a dynamic power supply for SRAM core array' [patent_app_type] => utility [patent_app_number] => 11/516994 [patent_app_country] => US [patent_app_date] => 2006-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 1926 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/394/07394714.pdf [firstpage_image] =>[orig_patent_app_number] => 11516994 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 834822 [patent_doc_number] => 07397707 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-07-08 [patent_title] => 'Compressed event counting technique and application to a flash memory system' [patent_app_type] => utility [patent_app_number] => 11/468661 [patent_app_country] => US [patent_app_date] => 2006-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 15250 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/397/07397707.pdf [firstpage_image] =>[orig_patent_app_number] => 11468661 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 342516 [patent_doc_number] => 07502274 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-03-10 [patent_title] => 'Apparatus and method for sensing target temperature' [patent_app_type] => utility [patent_app_number] => 11/481739 [patent_app_country] => US [patent_app_date] => 2006-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 3533 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/502/07502274.pdf [firstpage_image] =>[orig_patent_app_number] => 11481739 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5138951 [patent_doc_number] => 20070001167 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-01-04 [patent_title] => 'Storage device and semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/474944 [patent_app_country] => US [patent_app_date] => 2006-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 28 [patent_no_of_words] => 25253 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0001/20070001167.pdf [firstpage_image] =>[orig_patent_app_number] => 11474944 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5780672 [patent_doc_number] => 20060202723 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-09-14 [patent_title] => 'SYSTEMS AND METHODS THAT EMPLOY INDUCTIVE CURRENT STEERING FOR DIGITAL LOGIC CIRCUITS' [patent_app_type] => utility [patent_app_number] => 11/419027 [patent_app_country] => US [patent_app_date] => 2006-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 8070 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0202/20060202723.pdf [firstpage_image] =>[orig_patent_app_number] => 11419027 [rel_patent_id] =>[rel_patent_doc_number] =>)