
David Lam
Examiner (ID: 9389, Phone: (571)272-1782 , Office: P/2825 )
| Most Active Art Unit | 2827 |
| Art Unit(s) | 2818, 2827, 2825 |
| Total Applications | 2102 |
| Issued Applications | 2016 |
| Pending Applications | 28 |
| Abandoned Applications | 60 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 451399
[patent_doc_number] => 07251193
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-07-31
[patent_title] => 'Pseudo-dual port memory where ratio of first to second memory access is clock duty cycle independent'
[patent_app_type] => utility
[patent_app_number] => 11/282333
[patent_app_country] => US
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[patent_effective_date] => 0000-00-00
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/251/07251193.pdf
[firstpage_image] =>[orig_patent_app_number] => 11282333
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/282333 | Pseudo-dual port memory where ratio of first to second memory access is clock duty cycle independent | Nov 16, 2005 | Issued |
Array
(
[id] => 5654298
[patent_doc_number] => 20060140033
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[patent_kind] => A1
[patent_issue_date] => 2006-06-29
[patent_title] => 'Data bus architecture for a semiconductor memory'
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[firstpage_image] =>[orig_patent_app_number] => 11281932
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/281932 | Data bus architecture for a semiconductor memory | Nov 16, 2005 | Issued |
Array
(
[id] => 887699
[patent_doc_number] => 07352614
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[patent_kind] => B2
[patent_issue_date] => 2008-04-01
[patent_title] => 'Systems and methods for reading and writing a magnetic memory device'
[patent_app_type] => utility
[patent_app_number] => 11/281658
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/281658 | Systems and methods for reading and writing a magnetic memory device | Nov 16, 2005 | Issued |
Array
(
[id] => 5665877
[patent_doc_number] => 20060171227
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[patent_kind] => A1
[patent_issue_date] => 2006-08-03
[patent_title] => 'Low-voltage reading device in particular for MRAM memory'
[patent_app_type] => utility
[patent_app_number] => 11/281264
[patent_app_country] => US
[patent_app_date] => 2005-11-17
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/281264 | Low-voltage reading device in particular for MRAM memory | Nov 16, 2005 | Abandoned |
Array
(
[id] => 5589728
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[patent_issue_date] => 2006-02-23
[patent_title] => 'Low power circuits with small voltage swing transmission, voltage regeneration and wide bandwidth architecture'
[patent_app_type] => utility
[patent_app_number] => 11/248863
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[pdf_file] => publications/A1/0039/20060039179.pdf
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Array
(
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[firstpage_image] =>[orig_patent_app_number] => 11246164
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Array
(
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[patent_title] => 'Circuitry for and method of improving statistical distribution of integrated circuits'
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Array
(
[id] => 517405
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[patent_title] => 'Apparatus and method for providing a reprogrammable electrically programmable fuse'
[patent_app_type] => utility
[patent_app_number] => 11/246586
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[pdf_file] => patents/07/200/07200064.pdf
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/246586 | Apparatus and method for providing a reprogrammable electrically programmable fuse | Oct 6, 2005 | Issued |
Array
(
[id] => 5742170
[patent_doc_number] => 20060087895
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[patent_title] => 'Memory circuit with flexible bitline-related and/or wordline-related defect memory cell substitution'
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[patent_app_number] => 11/246046
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/246046 | Memory circuit with flexible bitline-related and/or wordline-related defect memory cell substitution | Oct 6, 2005 | Issued |
Array
(
[id] => 929158
[patent_doc_number] => 07315470
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[patent_issue_date] => 2008-01-01
[patent_title] => 'Data storage device and associated method for writing data to, and reading data from an unpatterned magnetic layer'
[patent_app_type] => utility
[patent_app_number] => 11/243360
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/243360 | Data storage device and associated method for writing data to, and reading data from an unpatterned magnetic layer | Oct 2, 2005 | Issued |
Array
(
[id] => 5825357
[patent_doc_number] => 20060062051
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[patent_title] => 'Memory device with unipolar and bipolar selectors'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/233464 | Memory device with unipolar and bipolar selectors | Sep 21, 2005 | Issued |
Array
(
[id] => 7590438
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[patent_title] => 'Die customization using programmable resistance memory elements'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/229955 | Die customization using programmable resistance memory elements | Sep 18, 2005 | Issued |
Array
(
[id] => 906016
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[patent_title] => 'Unified multilevel memory systems and methods'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/229191 | Unified multilevel memory systems and methods | Sep 14, 2005 | Issued |
Array
(
[id] => 5055551
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[patent_title] => 'Fuse structure for semiconductor device and controlling method thereof'
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Array
(
[id] => 542782
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Array
(
[id] => 684187
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Array
(
[id] => 6929039
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Array
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Array
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Array
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