Search

David Lam

Examiner (ID: 14034, Phone: (571)272-1782 , Office: P/2825 )

Most Active Art Unit
2827
Art Unit(s)
2825, 2827, 2818
Total Applications
2102
Issued Applications
2016
Pending Applications
28
Abandoned Applications
60

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 7263476 [patent_doc_number] => 20040151027 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-08-05 [patent_title] => 'Flash memory device with distributed coupling between array ground and substrate' [patent_app_type] => new [patent_app_number] => 10/758103 [patent_app_country] => US [patent_app_date] => 2004-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5752 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0151/20040151027.pdf [firstpage_image] =>[orig_patent_app_number] => 10758103 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/758103
Flash memory device with distributed coupling between array ground and substrate Jan 15, 2004 Issued
Array ( [id] => 7257194 [patent_doc_number] => 20040240277 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-12-02 [patent_title] => 'Semiconductor device' [patent_app_type] => new [patent_app_number] => 10/755333 [patent_app_country] => US [patent_app_date] => 2004-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 27 [patent_no_of_words] => 12320 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 290 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0240/20040240277.pdf [firstpage_image] =>[orig_patent_app_number] => 10755333 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/755333
Semiconductor device Jan 12, 2004 Issued
Array ( [id] => 701680 [patent_doc_number] => 07068531 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-06-27 [patent_title] => 'Bias-adjusted magnetoresistive devices for magnetic random access memory (MRAM) applications' [patent_app_type] => utility [patent_app_number] => 10/754935 [patent_app_country] => US [patent_app_date] => 2004-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 8211 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 39 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/068/07068531.pdf [firstpage_image] =>[orig_patent_app_number] => 10754935 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/754935
Bias-adjusted magnetoresistive devices for magnetic random access memory (MRAM) applications Jan 9, 2004 Issued
Array ( [id] => 7325230 [patent_doc_number] => 20040252558 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-12-16 [patent_title] => 'Semiconductor memory device including MOS transistor having a floating gate and a control gate' [patent_app_type] => new [patent_app_number] => 10/751430 [patent_app_country] => US [patent_app_date] => 2004-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 11235 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 334 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0252/20040252558.pdf [firstpage_image] =>[orig_patent_app_number] => 10751430 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/751430
Semiconductor memory device including MOS transistor having a floating gate and a control gate Jan 5, 2004 Issued
Array ( [id] => 7335112 [patent_doc_number] => 20040189352 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-09-30 [patent_title] => 'Data output buffer capable of controlling data valid window in semiconductor memory devices' [patent_app_type] => new [patent_app_number] => 10/749428 [patent_app_country] => US [patent_app_date] => 2003-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3557 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0189/20040189352.pdf [firstpage_image] =>[orig_patent_app_number] => 10749428 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/749428
Data output buffer capable of controlling data valid window in semiconductor memory devices Dec 30, 2003 Issued
Array ( [id] => 7073646 [patent_doc_number] => 20050146913 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-07-07 [patent_title] => 'Zero cancellation scheme to reduce plateline voltage in ferroelectric memory' [patent_app_type] => utility [patent_app_number] => 10/748041 [patent_app_country] => US [patent_app_date] => 2003-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 8438 [patent_no_of_claims] => 49 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0146/20050146913.pdf [firstpage_image] =>[orig_patent_app_number] => 10748041 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/748041
Zero cancellation scheme to reduce plateline voltage in ferroelectric memory Dec 28, 2003 Issued
Array ( [id] => 7368108 [patent_doc_number] => 20040218461 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-11-04 [patent_title] => 'Semiconductor device for domain crossing' [patent_app_type] => new [patent_app_number] => 10/748028 [patent_app_country] => US [patent_app_date] => 2003-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 6230 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0218/20040218461.pdf [firstpage_image] =>[orig_patent_app_number] => 10748028 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/748028
Semiconductor device for domain crossing Dec 28, 2003 Issued
Array ( [id] => 7121362 [patent_doc_number] => 20050013191 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-01-20 [patent_title] => 'Memory device having repeaters' [patent_app_type] => utility [patent_app_number] => 10/746032 [patent_app_country] => US [patent_app_date] => 2003-12-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 1483 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0013/20050013191.pdf [firstpage_image] =>[orig_patent_app_number] => 10746032 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/746032
Memory device having repeaters Dec 23, 2003 Issued
Array ( [id] => 7032284 [patent_doc_number] => 20050030793 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-02-10 [patent_title] => 'METHOD FOR OPERATING A NOR-ARRAY MEMORY MODULE COMPOSED OF P-TYPE MEMORY CELLS' [patent_app_type] => utility [patent_app_number] => 10/707564 [patent_app_country] => US [patent_app_date] => 2003-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 3316 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0030/20050030793.pdf [firstpage_image] =>[orig_patent_app_number] => 10707564 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/707564
Method for operating a NOR-array memory module composed of P-type memory cells Dec 21, 2003 Issued
Array ( [id] => 7032280 [patent_doc_number] => 20050030789 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-02-10 [patent_title] => 'METHOD FOR OPERATING A NAND-ARRAY MEMORY MODULE COMPOSED OF P-TYPE MEMORY CELLS' [patent_app_type] => utility [patent_app_number] => 10/707562 [patent_app_country] => US [patent_app_date] => 2003-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 3655 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0030/20050030789.pdf [firstpage_image] =>[orig_patent_app_number] => 10707562 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/707562
Method for operating a NAND-array memory module composed of P-type memory cells Dec 21, 2003 Issued
Array ( [id] => 670061 [patent_doc_number] => 07095644 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-08-22 [patent_title] => 'Conductive memory array having page mode and burst mode read capability' [patent_app_type] => utility [patent_app_number] => 10/745264 [patent_app_country] => US [patent_app_date] => 2003-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 24 [patent_no_of_words] => 12810 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/095/07095644.pdf [firstpage_image] =>[orig_patent_app_number] => 10745264 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/745264
Conductive memory array having page mode and burst mode read capability Dec 21, 2003 Issued
Array ( [id] => 788750 [patent_doc_number] => 06987684 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-01-17 [patent_title] => 'Content addressable memory (CAM) devices having multi-block error detection logic and entry selective error correction logic therein' [patent_app_type] => utility [patent_app_number] => 10/738264 [patent_app_country] => US [patent_app_date] => 2003-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 7596 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/987/06987684.pdf [firstpage_image] =>[orig_patent_app_number] => 10738264 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/738264
Content addressable memory (CAM) devices having multi-block error detection logic and entry selective error correction logic therein Dec 16, 2003 Issued
Array ( [id] => 964982 [patent_doc_number] => 06950370 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-09-27 [patent_title] => 'Synchronous memory device for preventing erroneous operation due to DQS ripple' [patent_app_type] => utility [patent_app_number] => 10/737230 [patent_app_country] => US [patent_app_date] => 2003-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 16 [patent_no_of_words] => 6942 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/950/06950370.pdf [firstpage_image] =>[orig_patent_app_number] => 10737230 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/737230
Synchronous memory device for preventing erroneous operation due to DQS ripple Dec 15, 2003 Issued
Array ( [id] => 7257065 [patent_doc_number] => 20040240248 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-12-02 [patent_title] => 'Ferroelectric register, and method for manufacturing capacitor of the same' [patent_app_type] => new [patent_app_number] => 10/734168 [patent_app_country] => US [patent_app_date] => 2003-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 4831 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0240/20040240248.pdf [firstpage_image] =>[orig_patent_app_number] => 10734168 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/734168
Ferroelectric register, and method for manufacturing capacitor of the same Dec 14, 2003 Issued
Array ( [id] => 1007161 [patent_doc_number] => 06906972 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-06-14 [patent_title] => 'Integrated DRAM semiconductor memory and method for operating the same' [patent_app_type] => utility [patent_app_number] => 10/733332 [patent_app_country] => US [patent_app_date] => 2003-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 2451 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/906/06906972.pdf [firstpage_image] =>[orig_patent_app_number] => 10733332 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/733332
Integrated DRAM semiconductor memory and method for operating the same Dec 11, 2003 Issued
Array ( [id] => 7619150 [patent_doc_number] => 06944039 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-09-13 [patent_title] => 'Content addressable memory with mode-selectable match detect timing' [patent_app_type] => utility [patent_app_number] => 10/734464 [patent_app_country] => US [patent_app_date] => 2003-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 6754 [patent_no_of_claims] => 46 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/944/06944039.pdf [firstpage_image] =>[orig_patent_app_number] => 10734464 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/734464
Content addressable memory with mode-selectable match detect timing Dec 11, 2003 Issued
Array ( [id] => 486970 [patent_doc_number] => 07221602 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-05-22 [patent_title] => 'Memory system comprising a semiconductor memory' [patent_app_type] => utility [patent_app_number] => 10/735250 [patent_app_country] => US [patent_app_date] => 2003-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6654 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 46 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/221/07221602.pdf [firstpage_image] =>[orig_patent_app_number] => 10735250 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/735250
Memory system comprising a semiconductor memory Dec 11, 2003 Issued
Array ( [id] => 7421360 [patent_doc_number] => 20040183198 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-09-23 [patent_title] => 'All-metal three-dimensional circuits and memories' [patent_app_type] => new [patent_app_number] => 10/731732 [patent_app_country] => US [patent_app_date] => 2003-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 30 [patent_no_of_words] => 18355 [patent_no_of_claims] => 44 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0183/20040183198.pdf [firstpage_image] =>[orig_patent_app_number] => 10731732 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/731732
All-metal three-dimensional circuits and memories Dec 7, 2003 Issued
Array ( [id] => 1023586 [patent_doc_number] => 06888745 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-05-03 [patent_title] => 'Nonvolatile memory device' [patent_app_type] => utility [patent_app_number] => 10/730190 [patent_app_country] => US [patent_app_date] => 2003-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 8112 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/888/06888745.pdf [firstpage_image] =>[orig_patent_app_number] => 10730190 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/730190
Nonvolatile memory device Dec 3, 2003 Issued
Array ( [id] => 7297852 [patent_doc_number] => 20040125674 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-07-01 [patent_title] => 'Semiconductor integrated circuit device' [patent_app_type] => new [patent_app_number] => 10/724364 [patent_app_country] => US [patent_app_date] => 2003-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2465 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0125/20040125674.pdf [firstpage_image] =>[orig_patent_app_number] => 10724364 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/724364
Semiconductor integrated circuit device Nov 30, 2003 Issued
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