Search

David Lam

Examiner (ID: 14034, Phone: (571)272-1782 , Office: P/2825 )

Most Active Art Unit
2827
Art Unit(s)
2825, 2827, 2818
Total Applications
2102
Issued Applications
2016
Pending Applications
28
Abandoned Applications
60

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4359249 [patent_doc_number] => 06285622 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-04 [patent_title] => 'Semiconductor device' [patent_app_type] => 1 [patent_app_number] => 9/698036 [patent_app_country] => US [patent_app_date] => 2000-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 10198 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 197 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/285/06285622.pdf [firstpage_image] =>[orig_patent_app_number] => 698036 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/698036
Semiconductor device Oct 29, 2000 Issued
Array ( [id] => 4318186 [patent_doc_number] => 06327212 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-12-04 [patent_title] => 'Microcomputer and microprocessor having flash memory operable from single external power supply' [patent_app_type] => 1 [patent_app_number] => 9/694487 [patent_app_country] => US [patent_app_date] => 2000-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 31 [patent_no_of_words] => 14105 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/327/06327212.pdf [firstpage_image] =>[orig_patent_app_number] => 694487 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/694487
Microcomputer and microprocessor having flash memory operable from single external power supply Oct 23, 2000 Issued
Array ( [id] => 1546802 [patent_doc_number] => 06373742 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-16 [patent_title] => 'Two side decoding of a memory array' [patent_app_type] => B1 [patent_app_number] => 09/689036 [patent_app_country] => US [patent_app_date] => 2000-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 3565 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/373/06373742.pdf [firstpage_image] =>[orig_patent_app_number] => 09689036 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/689036
Two side decoding of a memory array Oct 11, 2000 Issued
Array ( [id] => 4342107 [patent_doc_number] => 06320808 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-20 [patent_title] => 'Memory read amplifier circuit with high current level discrimination capacity' [patent_app_type] => 1 [patent_app_number] => 9/686632 [patent_app_country] => US [patent_app_date] => 2000-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 2824 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 258 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/320/06320808.pdf [firstpage_image] =>[orig_patent_app_number] => 686632 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/686632
Memory read amplifier circuit with high current level discrimination capacity Oct 10, 2000 Issued
Array ( [id] => 4283087 [patent_doc_number] => 06307776 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-23 [patent_title] => 'Multi-bit-per-cell flash EEPROM memory with refresh' [patent_app_type] => 1 [patent_app_number] => 9/680797 [patent_app_country] => US [patent_app_date] => 2000-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 6895 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/307/06307776.pdf [firstpage_image] =>[orig_patent_app_number] => 680797 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/680797
Multi-bit-per-cell flash EEPROM memory with refresh Oct 5, 2000 Issued
Array ( [id] => 4287013 [patent_doc_number] => 06324117 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-27 [patent_title] => 'Method of selecting a memory access line and an access line decoder for performing the same' [patent_app_type] => 1 [patent_app_number] => 9/676434 [patent_app_country] => US [patent_app_date] => 2000-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 13 [patent_no_of_words] => 6941 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 40 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/324/06324117.pdf [firstpage_image] =>[orig_patent_app_number] => 676434 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/676434
Method of selecting a memory access line and an access line decoder for performing the same Sep 28, 2000 Issued
Array ( [id] => 1520430 [patent_doc_number] => 06501684 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-12-31 [patent_title] => 'Integrated circuit having an EEPROM and flash EPROM' [patent_app_type] => B1 [patent_app_number] => 09/668431 [patent_app_country] => US [patent_app_date] => 2000-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3745 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/501/06501684.pdf [firstpage_image] =>[orig_patent_app_number] => 09668431 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/668431
Integrated circuit having an EEPROM and flash EPROM Sep 21, 2000 Issued
Array ( [id] => 1480106 [patent_doc_number] => 06345001 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-02-05 [patent_title] => 'Compressed event counting technique and application to a flash memory system' [patent_app_type] => B1 [patent_app_number] => 09/662032 [patent_app_country] => US [patent_app_date] => 2000-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 10310 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 40 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/345/06345001.pdf [firstpage_image] =>[orig_patent_app_number] => 09662032 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/662032
Compressed event counting technique and application to a flash memory system Sep 13, 2000 Issued
Array ( [id] => 4317958 [patent_doc_number] => 06327197 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-12-04 [patent_title] => 'Structure and method of a column redundancy memory' [patent_app_type] => 1 [patent_app_number] => 9/660534 [patent_app_country] => US [patent_app_date] => 2000-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 1850 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/327/06327197.pdf [firstpage_image] =>[orig_patent_app_number] => 660534 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/660534
Structure and method of a column redundancy memory Sep 12, 2000 Issued
Array ( [id] => 4342131 [patent_doc_number] => 06320810 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-20 [patent_title] => 'Semiconductor memory device allowing reduction in current consumption' [patent_app_type] => 1 [patent_app_number] => 9/659832 [patent_app_country] => US [patent_app_date] => 2000-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 15 [patent_no_of_words] => 11440 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/320/06320810.pdf [firstpage_image] =>[orig_patent_app_number] => 659832 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/659832
Semiconductor memory device allowing reduction in current consumption Sep 10, 2000 Issued
Array ( [id] => 4283115 [patent_doc_number] => 06307778 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-23 [patent_title] => 'Non volatile memory with detection of short circuits between word lines' [patent_app_type] => 1 [patent_app_number] => 9/658236 [patent_app_country] => US [patent_app_date] => 2000-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 3078 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/307/06307778.pdf [firstpage_image] =>[orig_patent_app_number] => 658236 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/658236
Non volatile memory with detection of short circuits between word lines Sep 7, 2000 Issued
Array ( [id] => 4380861 [patent_doc_number] => 06275418 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-14 [patent_title] => 'Circuit with non-volatile memory and method of erasing the memory a number of bits at a time' [patent_app_type] => 1 [patent_app_number] => 9/656834 [patent_app_country] => US [patent_app_date] => 2000-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 3804 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/275/06275418.pdf [firstpage_image] =>[orig_patent_app_number] => 656834 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/656834
Circuit with non-volatile memory and method of erasing the memory a number of bits at a time Sep 6, 2000 Issued
Array ( [id] => 4381076 [patent_doc_number] => 06275433 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-14 [patent_title] => 'Four transistor SRAM cell with improved read access' [patent_app_type] => 1 [patent_app_number] => 9/651632 [patent_app_country] => US [patent_app_date] => 2000-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 7491 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/275/06275433.pdf [firstpage_image] =>[orig_patent_app_number] => 651632 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/651632
Four transistor SRAM cell with improved read access Aug 29, 2000 Issued
Array ( [id] => 1565191 [patent_doc_number] => 06363013 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-26 [patent_title] => 'Auto-stopped page soft-programming method with voltage limited component' [patent_app_type] => B1 [patent_app_number] => 09/652230 [patent_app_country] => US [patent_app_date] => 2000-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5334 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/363/06363013.pdf [firstpage_image] =>[orig_patent_app_number] => 09652230 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/652230
Auto-stopped page soft-programming method with voltage limited component Aug 28, 2000 Issued
Array ( [id] => 4318050 [patent_doc_number] => 06327202 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-12-04 [patent_title] => 'Bit line pre-charge in a memory' [patent_app_type] => 1 [patent_app_number] => 9/648701 [patent_app_country] => US [patent_app_date] => 2000-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 7149 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/327/06327202.pdf [firstpage_image] =>[orig_patent_app_number] => 648701 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/648701
Bit line pre-charge in a memory Aug 24, 2000 Issued
Array ( [id] => 4381259 [patent_doc_number] => 06275446 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-14 [patent_title] => 'Clock generation circuits and methods' [patent_app_type] => 1 [patent_app_number] => 9/648703 [patent_app_country] => US [patent_app_date] => 2000-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 8612 [patent_no_of_claims] => 53 [patent_no_of_ind_claims] => 25 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/275/06275446.pdf [firstpage_image] =>[orig_patent_app_number] => 648703 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/648703
Clock generation circuits and methods Aug 24, 2000 Issued
Array ( [id] => 4374112 [patent_doc_number] => 06256243 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-03 [patent_title] => 'Test circuit for testing a digital semiconductor circuit configuration' [patent_app_type] => 1 [patent_app_number] => 9/642734 [patent_app_country] => US [patent_app_date] => 2000-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 4995 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/256/06256243.pdf [firstpage_image] =>[orig_patent_app_number] => 642734 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/642734
Test circuit for testing a digital semiconductor circuit configuration Aug 16, 2000 Issued
Array ( [id] => 1409891 [patent_doc_number] => 06545891 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-04-08 [patent_title] => 'Modular memory device' [patent_app_type] => B1 [patent_app_number] => 09/638334 [patent_app_country] => US [patent_app_date] => 2000-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 3618 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/545/06545891.pdf [firstpage_image] =>[orig_patent_app_number] => 09638334 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/638334
Modular memory device Aug 13, 2000 Issued
Array ( [id] => 1465186 [patent_doc_number] => 06351412 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-02-26 [patent_title] => 'Memory card' [patent_app_type] => B1 [patent_app_number] => 09/636736 [patent_app_country] => US [patent_app_date] => 2000-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 6198 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/351/06351412.pdf [firstpage_image] =>[orig_patent_app_number] => 09636736 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/636736
Memory card Aug 10, 2000 Issued
Array ( [id] => 4384510 [patent_doc_number] => 06288959 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-11 [patent_title] => 'Controlling the precharge operation in a DRAM array in a SRAM interface' [patent_app_type] => 1 [patent_app_number] => 9/632232 [patent_app_country] => US [patent_app_date] => 2000-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 5582 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/288/06288959.pdf [firstpage_image] =>[orig_patent_app_number] => 632232 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/632232
Controlling the precharge operation in a DRAM array in a SRAM interface Aug 3, 2000 Issued
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