David Lam

Array ( [id] => 4298749 [patent_doc_number] => 06269046 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-31 [patent_title] => 'Semiconductor memory device having improved decoders for decoding row and column address signals' [patent_app_type] => 1 [patent_app_number] => 9/533530 [patent_app_country] => US [patent_app_date] => 2000-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 5689 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/269/06269046.pdf [firstpage_image] =>[orig_patent_app_number] => 533530 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4395140 [patent_doc_number] => 06278628 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-21 [patent_title] => 'Semiconductor integrated circuit' [patent_app_type] => 1 [patent_app_number] => 9/532734 [patent_app_country] => US [patent_app_date] => 2000-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 23 [patent_no_of_words] => 8752 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/278/06278628.pdf [firstpage_image] =>[orig_patent_app_number] => 532734 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4363903 [patent_doc_number] => 06215724 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-10 [patent_title] => 'Circuit and method for eliminating idle cycles in a memory device' [patent_app_type] => 1 [patent_app_number] => 9/525868 [patent_app_country] => US [patent_app_date] => 2000-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 14 [patent_no_of_words] => 6526 [patent_no_of_claims] => 51 [patent_no_of_ind_claims] => 24 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/215/06215724.pdf [firstpage_image] =>[orig_patent_app_number] => 525868 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4417054 [patent_doc_number] => 06233197 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-15 [patent_title] => 'Multi-port semiconductor memory and compiler having capacitance compensation' [patent_app_type] => 1 [patent_app_number] => 9/524734 [patent_app_country] => US [patent_app_date] => 2000-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 6059 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/233/06233197.pdf [firstpage_image] =>[orig_patent_app_number] => 524734 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4286982 [patent_doc_number] => 06324115 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-27 [patent_title] => 'Semiconductor memory device with burst mode access' [patent_app_type] => 1 [patent_app_number] => 9/520730 [patent_app_country] => US [patent_app_date] => 2000-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8297 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/324/06324115.pdf [firstpage_image] =>[orig_patent_app_number] => 520730 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1291939 [patent_doc_number] => 06639835 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-10-28 [patent_title] => 'Static NVRAM with ultra thin tunnel oxides' [patent_app_type] => B2 [patent_app_number] => 09/515630 [patent_app_country] => US [patent_app_date] => 2000-02-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 18 [patent_no_of_words] => 9179 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/639/06639835.pdf [firstpage_image] =>[orig_patent_app_number] => 09515630 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4309377 [patent_doc_number] => 06198681 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-06 [patent_title] => 'Sense amplifier for low voltage memory arrays' [patent_app_type] => 1 [patent_app_number] => 9/513936 [patent_app_country] => US [patent_app_date] => 2000-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 7245 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/198/06198681.pdf [firstpage_image] =>[orig_patent_app_number] => 513936 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4309535 [patent_doc_number] => 06198691 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-06 [patent_title] => 'Force page paging scheme for microcontrollers of various sizes using data random access memory' [patent_app_type] => 1 [patent_app_number] => 9/513427 [patent_app_country] => US [patent_app_date] => 2000-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 2224 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/198/06198691.pdf [firstpage_image] =>[orig_patent_app_number] => 513427 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1517703 [patent_doc_number] => 06421291 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-16 [patent_title] => 'Semiconductor memory device having high data input/output frequency and capable of efficiently testing circuit associated with data input/output' [patent_app_type] => B1 [patent_app_number] => 09/510532 [patent_app_country] => US [patent_app_date] => 2000-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 18 [patent_no_of_words] => 9807 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/421/06421291.pdf [firstpage_image] =>[orig_patent_app_number] => 09510532 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4331411 [patent_doc_number] => 06249473 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-19 [patent_title] => 'Power down system for regulated internal voltage supply in DRAM' [patent_app_type] => 1 [patent_app_number] => 9/510436 [patent_app_country] => US [patent_app_date] => 2000-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 2358 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/249/06249473.pdf [firstpage_image] =>[orig_patent_app_number] => 510436 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1425263 [patent_doc_number] => 06512706 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-01-28 [patent_title] => 'System and method for writing to a register file' [patent_app_type] => B1 [patent_app_number] => 09/493336 [patent_app_country] => US [patent_app_date] => 2000-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 8962 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/512/06512706.pdf [firstpage_image] =>[orig_patent_app_number] => 09493336 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4305181 [patent_doc_number] => 06236603 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-22 [patent_title] => 'High speed charging of core cell drain lines in a memory device' [patent_app_type] => 1 [patent_app_number] => 9/489232 [patent_app_country] => US [patent_app_date] => 2000-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 3537 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/236/06236603.pdf [firstpage_image] =>[orig_patent_app_number] => 489232 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4363891 [patent_doc_number] => 06215723 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-10 [patent_title] => 'Semiconductor memory device having sequentially disabling activated word lines' [patent_app_type] => 1 [patent_app_number] => 9/489236 [patent_app_country] => US [patent_app_date] => 2000-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 5778 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/215/06215723.pdf [firstpage_image] =>[orig_patent_app_number] => 489236 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4419991 [patent_doc_number] => 06266274 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-24 [patent_title] => 'Semiconductor memory with non-volatile two-transistor memory cells' [patent_app_type] => 1 [patent_app_number] => 9/483734 [patent_app_country] => US [patent_app_date] => 2000-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 6133 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/266/06266274.pdf [firstpage_image] =>[orig_patent_app_number] => 483734 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4331148 [patent_doc_number] => 06249455 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-19 [patent_title] => 'Multi-step pulse generating circuit for flash memory' [patent_app_type] => 1 [patent_app_number] => 9/468634 [patent_app_country] => US [patent_app_date] => 1999-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2675 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/249/06249455.pdf [firstpage_image] =>[orig_patent_app_number] => 468634 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4309639 [patent_doc_number] => 06185129 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-06 [patent_title] => 'Power reset circuit of a flash memory device' [patent_app_type] => 1 [patent_app_number] => 9/468934 [patent_app_country] => US [patent_app_date] => 1999-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3834 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/185/06185129.pdf [firstpage_image] =>[orig_patent_app_number] => 468934 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4417603 [patent_doc_number] => 06172926 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-09 [patent_title] => 'Optical data storage devices and methods' [patent_app_type] => 1 [patent_app_number] => 9/465636 [patent_app_country] => US [patent_app_date] => 1999-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 3434 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/172/06172926.pdf [firstpage_image] =>[orig_patent_app_number] => 465636 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4373733 [patent_doc_number] => 06256218 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-03 [patent_title] => 'Integrated circuit memory devices having adjacent input/output buffers and shift blocks' [patent_app_type] => 1 [patent_app_number] => 9/466536 [patent_app_country] => US [patent_app_date] => 1999-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4992 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/256/06256218.pdf [firstpage_image] =>[orig_patent_app_number] => 466536 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4145534 [patent_doc_number] => 06147921 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-14 [patent_title] => 'Method and apparatus for optimizing memory performance with opportunistic refreshing' [patent_app_type] => 1 [patent_app_number] => 9/464437 [patent_app_country] => US [patent_app_date] => 1999-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5546 [patent_no_of_claims] => 48 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/147/06147921.pdf [firstpage_image] =>[orig_patent_app_number] => 464437 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4331277 [patent_doc_number] => 06249464 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-19 [patent_title] => 'Block redundancy in ultra low power memory circuits' [patent_app_type] => 1 [patent_app_number] => 9/461632 [patent_app_country] => US [patent_app_date] => 1999-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 2408 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 29 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/249/06249464.pdf [firstpage_image] =>[orig_patent_app_number] => 461632 [rel_patent_id] =>[rel_patent_doc_number] =>)