Search

David Lam

Examiner (ID: 14034, Phone: (571)272-1782 , Office: P/2825 )

Most Active Art Unit
2827
Art Unit(s)
2825, 2827, 2818
Total Applications
2102
Issued Applications
2016
Pending Applications
28
Abandoned Applications
60

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4419403 [patent_doc_number] => 06301177 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-09 [patent_title] => 'Internal power supply voltage generating circuit and the method for controlling thereof' [patent_app_type] => 1 [patent_app_number] => 9/457576 [patent_app_country] => US [patent_app_date] => 1999-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2998 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/301/06301177.pdf [firstpage_image] =>[orig_patent_app_number] => 457576 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/457576
Internal power supply voltage generating circuit and the method for controlling thereof Dec 8, 1999 Issued
Array ( [id] => 4331162 [patent_doc_number] => 06249456 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-19 [patent_title] => 'Secured EEPROM memory comprising means for the detection of erasure by ultraviolet radiation' [patent_app_type] => 1 [patent_app_number] => 9/448632 [patent_app_country] => US [patent_app_date] => 1999-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 1651 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/249/06249456.pdf [firstpage_image] =>[orig_patent_app_number] => 448632 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/448632
Secured EEPROM memory comprising means for the detection of erasure by ultraviolet radiation Nov 23, 1999 Issued
Array ( [id] => 4393744 [patent_doc_number] => 06295227 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-25 [patent_title] => 'Non-volatile semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 9/449932 [patent_app_country] => US [patent_app_date] => 1999-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 47 [patent_figures_cnt] => 50 [patent_no_of_words] => 11233 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/295/06295227.pdf [firstpage_image] =>[orig_patent_app_number] => 449932 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/449932
Non-volatile semiconductor memory device Nov 23, 1999 Issued
Array ( [id] => 1507353 [patent_doc_number] => 06466481 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-15 [patent_title] => 'Device and method for programming nonvolatile memory cells with automatic generation of programming voltage' [patent_app_type] => B1 [patent_app_number] => 09/438232 [patent_app_country] => US [patent_app_date] => 1999-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3416 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 12 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/466/06466481.pdf [firstpage_image] =>[orig_patent_app_number] => 09438232 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/438232
Device and method for programming nonvolatile memory cells with automatic generation of programming voltage Nov 11, 1999 Issued
Array ( [id] => 4273189 [patent_doc_number] => 06259624 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-10 [patent_title] => 'Nonvolatile semiconductor storage device and data writing method thereof' [patent_app_type] => 1 [patent_app_number] => 9/435632 [patent_app_country] => US [patent_app_date] => 1999-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 20367 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/259/06259624.pdf [firstpage_image] =>[orig_patent_app_number] => 435632 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/435632
Nonvolatile semiconductor storage device and data writing method thereof Nov 7, 1999 Issued
Array ( [id] => 4152955 [patent_doc_number] => 06107134 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-22 [patent_title] => 'High performance DRAM structure employing multiple thickness gate oxide' [patent_app_type] => 1 [patent_app_number] => 9/431134 [patent_app_country] => US [patent_app_date] => 1999-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 5166 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/107/06107134.pdf [firstpage_image] =>[orig_patent_app_number] => 431134 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/431134
High performance DRAM structure employing multiple thickness gate oxide Oct 31, 1999 Issued
Array ( [id] => 4110363 [patent_doc_number] => 06097641 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-01 [patent_title] => 'High performance DRAM structure employing multiple thickness gate oxide' [patent_app_type] => 1 [patent_app_number] => 9/431132 [patent_app_country] => US [patent_app_date] => 1999-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 5166 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/097/06097641.pdf [firstpage_image] =>[orig_patent_app_number] => 431132 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/431132
High performance DRAM structure employing multiple thickness gate oxide Oct 31, 1999 Issued
Array ( [id] => 4145317 [patent_doc_number] => 06147907 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-14 [patent_title] => 'Biasing scheme to reduce stress on non-selected cells during read' [patent_app_type] => 1 [patent_app_number] => 9/430336 [patent_app_country] => US [patent_app_date] => 1999-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 3254 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/147/06147907.pdf [firstpage_image] =>[orig_patent_app_number] => 430336 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/430336
Biasing scheme to reduce stress on non-selected cells during read Oct 28, 1999 Issued
Array ( [id] => 4252265 [patent_doc_number] => 06166965 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-26 [patent_title] => 'Semiconductor memory device having push-pull type output circuit formed by two N-channel MOS transistors' [patent_app_type] => 1 [patent_app_number] => 9/431334 [patent_app_country] => US [patent_app_date] => 1999-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 32 [patent_no_of_words] => 4837 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 210 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/166/06166965.pdf [firstpage_image] =>[orig_patent_app_number] => 431334 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/431334
Semiconductor memory device having push-pull type output circuit formed by two N-channel MOS transistors Oct 27, 1999 Issued
Array ( [id] => 4363403 [patent_doc_number] => 06215691 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-10 [patent_title] => 'Cell structure of ferroelectric memory device' [patent_app_type] => 1 [patent_app_number] => 9/425030 [patent_app_country] => US [patent_app_date] => 1999-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 1902 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/215/06215691.pdf [firstpage_image] =>[orig_patent_app_number] => 425030 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/425030
Cell structure of ferroelectric memory device Oct 24, 1999 Issued
Array ( [id] => 4416744 [patent_doc_number] => 06233171 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-15 [patent_title] => 'Superconducting magnetoresistive memory element using controlled exchange interaction' [patent_app_type] => 1 [patent_app_number] => 9/422135 [patent_app_country] => US [patent_app_date] => 1999-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3164 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/233/06233171.pdf [firstpage_image] =>[orig_patent_app_number] => 422135 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/422135
Superconducting magnetoresistive memory element using controlled exchange interaction Oct 19, 1999 Issued
Array ( [id] => 4250737 [patent_doc_number] => 06144606 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-07 [patent_title] => 'Method and system for bi-directional voltage regulation detection' [patent_app_type] => 1 [patent_app_number] => 9/417732 [patent_app_country] => US [patent_app_date] => 1999-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 6484 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/144/06144606.pdf [firstpage_image] =>[orig_patent_app_number] => 417732 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/417732
Method and system for bi-directional voltage regulation detection Oct 13, 1999 Issued
Array ( [id] => 4170427 [patent_doc_number] => 06104661 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-15 [patent_title] => 'Semiconductor memory with local phase generation from global phase signals and local isolation signals' [patent_app_type] => 1 [patent_app_number] => 9/416711 [patent_app_country] => US [patent_app_date] => 1999-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 1593 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/104/06104661.pdf [firstpage_image] =>[orig_patent_app_number] => 416711 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/416711
Semiconductor memory with local phase generation from global phase signals and local isolation signals Oct 11, 1999 Issued
Array ( [id] => 4369678 [patent_doc_number] => 06219300 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-17 [patent_title] => 'Semiconductor device' [patent_app_type] => 1 [patent_app_number] => 9/411836 [patent_app_country] => US [patent_app_date] => 1999-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 24 [patent_no_of_words] => 9168 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 212 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/219/06219300.pdf [firstpage_image] =>[orig_patent_app_number] => 411836 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/411836
Semiconductor device Oct 3, 1999 Issued
Array ( [id] => 4185246 [patent_doc_number] => 06141250 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-31 [patent_title] => 'Non-volatile semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 9/409432 [patent_app_country] => US [patent_app_date] => 1999-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 35 [patent_no_of_words] => 16219 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 255 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/141/06141250.pdf [firstpage_image] =>[orig_patent_app_number] => 409432 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/409432
Non-volatile semiconductor memory device Sep 29, 1999 Issued
Array ( [id] => 4342083 [patent_doc_number] => 06320806 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-20 [patent_title] => 'Input/output line precharge circuit and semiconductor memory device adopting the same' [patent_app_type] => 1 [patent_app_number] => 9/399934 [patent_app_country] => US [patent_app_date] => 1999-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 4035 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/320/06320806.pdf [firstpage_image] =>[orig_patent_app_number] => 399934 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/399934
Input/output line precharge circuit and semiconductor memory device adopting the same Sep 20, 1999 Issued
Array ( [id] => 4425591 [patent_doc_number] => 06178134 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-23 [patent_title] => 'Static random access memory with global bit-lines' [patent_app_type] => 1 [patent_app_number] => 9/401032 [patent_app_country] => US [patent_app_date] => 1999-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 4164 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/178/06178134.pdf [firstpage_image] =>[orig_patent_app_number] => 401032 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/401032
Static random access memory with global bit-lines Sep 20, 1999 Issued
Array ( [id] => 4202469 [patent_doc_number] => 06154412 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-28 [patent_title] => 'Microcomputer and microprocessor having flash memory operable from single external power supply' [patent_app_type] => 1 [patent_app_number] => 9/397851 [patent_app_country] => US [patent_app_date] => 1999-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 31 [patent_no_of_words] => 14111 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/154/06154412.pdf [firstpage_image] =>[orig_patent_app_number] => 397851 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/397851
Microcomputer and microprocessor having flash memory operable from single external power supply Sep 16, 1999 Issued
Array ( [id] => 4425531 [patent_doc_number] => 06195277 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-27 [patent_title] => 'Multiple signal detection circuit' [patent_app_type] => 1 [patent_app_number] => 9/394232 [patent_app_country] => US [patent_app_date] => 1999-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 6890 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/195/06195277.pdf [firstpage_image] =>[orig_patent_app_number] => 394232 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/394232
Multiple signal detection circuit Sep 12, 1999 Issued
Array ( [id] => 4117169 [patent_doc_number] => 06101140 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-08 [patent_title] => 'Sense amplifier driver circuit for supplying a reduced driving voltage to sense amplifier' [patent_app_type] => 1 [patent_app_number] => 9/372976 [patent_app_country] => US [patent_app_date] => 1999-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 10340 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 206 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/101/06101140.pdf [firstpage_image] =>[orig_patent_app_number] => 372976 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/372976
Sense amplifier driver circuit for supplying a reduced driving voltage to sense amplifier Aug 11, 1999 Issued
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