Search

David Lam

Examiner (ID: 14034, Phone: (571)272-1782 , Office: P/2825 )

Most Active Art Unit
2827
Art Unit(s)
2825, 2827, 2818
Total Applications
2102
Issued Applications
2016
Pending Applications
28
Abandoned Applications
60

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4331474 [patent_doc_number] => 06249477 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-19 [patent_title] => 'Semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 9/373177 [patent_app_country] => US [patent_app_date] => 1999-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 20 [patent_no_of_words] => 8441 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/249/06249477.pdf [firstpage_image] =>[orig_patent_app_number] => 373177 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/373177
Semiconductor memory device Aug 11, 1999 Issued
Array ( [id] => 4416713 [patent_doc_number] => 06233168 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-15 [patent_title] => 'Non-volatile semiconductor memory capable of reducing parasitic current' [patent_app_type] => 1 [patent_app_number] => 9/371834 [patent_app_country] => US [patent_app_date] => 1999-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 8448 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 221 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/233/06233168.pdf [firstpage_image] =>[orig_patent_app_number] => 371834 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/371834
Non-volatile semiconductor memory capable of reducing parasitic current Aug 10, 1999 Issued
Array ( [id] => 4372281 [patent_doc_number] => 06191976 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-20 [patent_title] => 'Flash memory margin mode enhancements' [patent_app_type] => 1 [patent_app_number] => 9/372730 [patent_app_country] => US [patent_app_date] => 1999-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 3900 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/191/06191976.pdf [firstpage_image] =>[orig_patent_app_number] => 372730 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/372730
Flash memory margin mode enhancements Aug 10, 1999 Issued
Array ( [id] => 4247328 [patent_doc_number] => 06118706 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-12 [patent_title] => 'Flash memory block or sector clear operation' [patent_app_type] => 1 [patent_app_number] => 9/373436 [patent_app_country] => US [patent_app_date] => 1999-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 16 [patent_no_of_words] => 4870 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 207 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/118/06118706.pdf [firstpage_image] =>[orig_patent_app_number] => 373436 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/373436
Flash memory block or sector clear operation Aug 10, 1999 Issued
Array ( [id] => 4417413 [patent_doc_number] => 06172909 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-09 [patent_title] => 'Ramped gate technique for soft programming to tighten the Vt distribution' [patent_app_type] => 1 [patent_app_number] => 9/370380 [patent_app_country] => US [patent_app_date] => 1999-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 6569 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/172/06172909.pdf [firstpage_image] =>[orig_patent_app_number] => 370380 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/370380
Ramped gate technique for soft programming to tighten the Vt distribution Aug 8, 1999 Issued
Array ( [id] => 4316871 [patent_doc_number] => 06188607 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-13 [patent_title] => 'Integrated circuit memory having divided-well architecture' [patent_app_type] => 1 [patent_app_number] => 9/366978 [patent_app_country] => US [patent_app_date] => 1999-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 2144 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/188/06188607.pdf [firstpage_image] =>[orig_patent_app_number] => 366978 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/366978
Integrated circuit memory having divided-well architecture Aug 3, 1999 Issued
Array ( [id] => 4170061 [patent_doc_number] => 06108251 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-22 [patent_title] => 'Method and apparatus for remapping memory addresses for redundancy' [patent_app_type] => 1 [patent_app_number] => 9/364947 [patent_app_country] => US [patent_app_date] => 1999-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 13 [patent_no_of_words] => 4340 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/108/06108251.pdf [firstpage_image] =>[orig_patent_app_number] => 364947 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/364947
Method and apparatus for remapping memory addresses for redundancy Jul 29, 1999 Issued
Array ( [id] => 4197978 [patent_doc_number] => 06151267 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-21 [patent_title] => 'Memory device with decoder having simplified structure' [patent_app_type] => 1 [patent_app_number] => 9/364077 [patent_app_country] => US [patent_app_date] => 1999-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 5758 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/151/06151267.pdf [firstpage_image] =>[orig_patent_app_number] => 364077 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/364077
Memory device with decoder having simplified structure Jul 29, 1999 Issued
Array ( [id] => 4317365 [patent_doc_number] => 06188642 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-13 [patent_title] => 'Integrated memory having column decoder for addressing corresponding bit line' [patent_app_type] => 1 [patent_app_number] => 9/348736 [patent_app_country] => US [patent_app_date] => 1999-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3969 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/188/06188642.pdf [firstpage_image] =>[orig_patent_app_number] => 348736 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/348736
Integrated memory having column decoder for addressing corresponding bit line Jul 5, 1999 Issued
Array ( [id] => 4261913 [patent_doc_number] => 06137739 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-24 [patent_title] => 'Multilevel sensing circuit and method thereof' [patent_app_type] => 1 [patent_app_number] => 9/342176 [patent_app_country] => US [patent_app_date] => 1999-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 93 [patent_no_of_words] => 5819 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/137/06137739.pdf [firstpage_image] =>[orig_patent_app_number] => 342176 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/342176
Multilevel sensing circuit and method thereof Jun 28, 1999 Issued
Array ( [id] => 4246287 [patent_doc_number] => 06075747 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-13 [patent_title] => 'Method of controlling a row address strobe path' [patent_app_type] => 1 [patent_app_number] => 9/342177 [patent_app_country] => US [patent_app_date] => 1999-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 1732 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/075/06075747.pdf [firstpage_image] =>[orig_patent_app_number] => 342177 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/342177
Method of controlling a row address strobe path Jun 28, 1999 Issued
Array ( [id] => 4317034 [patent_doc_number] => 06188619 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-13 [patent_title] => 'Memory device with address translation for skipping failed memory blocks' [patent_app_type] => 1 [patent_app_number] => 9/339377 [patent_app_country] => US [patent_app_date] => 1999-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3930 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/188/06188619.pdf [firstpage_image] =>[orig_patent_app_number] => 339377 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/339377
Memory device with address translation for skipping failed memory blocks Jun 23, 1999 Issued
Array ( [id] => 4245886 [patent_doc_number] => 06075719 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-13 [patent_title] => 'Method of programming phase-change memory element' [patent_app_type] => 1 [patent_app_number] => 9/337778 [patent_app_country] => US [patent_app_date] => 1999-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4262 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/075/06075719.pdf [firstpage_image] =>[orig_patent_app_number] => 337778 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/337778
Method of programming phase-change memory element Jun 21, 1999 Issued
Array ( [id] => 4197950 [patent_doc_number] => 06151265 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-21 [patent_title] => 'Memory device having direct sense circuit' [patent_app_type] => 1 [patent_app_number] => 9/332876 [patent_app_country] => US [patent_app_date] => 1999-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 23 [patent_no_of_words] => 6716 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/151/06151265.pdf [firstpage_image] =>[orig_patent_app_number] => 332876 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/332876
Memory device having direct sense circuit Jun 14, 1999 Issued
Array ( [id] => 4417593 [patent_doc_number] => 06172925 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-09 [patent_title] => 'Memory array bitline timing circuit' [patent_app_type] => 1 [patent_app_number] => 9/333178 [patent_app_country] => US [patent_app_date] => 1999-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3418 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/172/06172925.pdf [firstpage_image] =>[orig_patent_app_number] => 333178 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/333178
Memory array bitline timing circuit Jun 13, 1999 Issued
Array ( [id] => 4145421 [patent_doc_number] => 06147914 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-14 [patent_title] => 'On-chip word line voltage generation for DRAM embedded in logic process' [patent_app_type] => 1 [patent_app_number] => 9/332757 [patent_app_country] => US [patent_app_date] => 1999-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 21 [patent_no_of_words] => 10811 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/147/06147914.pdf [firstpage_image] =>[orig_patent_app_number] => 332757 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/332757
On-chip word line voltage generation for DRAM embedded in logic process Jun 13, 1999 Issued
Array ( [id] => 4250533 [patent_doc_number] => 06144592 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-07 [patent_title] => 'Semiconductor memory device having a redundant memory' [patent_app_type] => 1 [patent_app_number] => 9/327179 [patent_app_country] => US [patent_app_date] => 1999-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 15 [patent_no_of_words] => 10744 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/144/06144592.pdf [firstpage_image] =>[orig_patent_app_number] => 327179 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/327179
Semiconductor memory device having a redundant memory Jun 6, 1999 Issued
Array ( [id] => 4261997 [patent_doc_number] => 06137745 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-24 [patent_title] => 'Embedded memory control circuit for control of access operations to a memory module' [patent_app_type] => 1 [patent_app_number] => 9/322078 [patent_app_country] => US [patent_app_date] => 1999-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 3559 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 208 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/137/06137745.pdf [firstpage_image] =>[orig_patent_app_number] => 322078 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/322078
Embedded memory control circuit for control of access operations to a memory module May 26, 1999 Issued
Array ( [id] => 4216746 [patent_doc_number] => 06078519 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-20 [patent_title] => 'Semiconductor device, data processing system and a method for changing threshold of a non-volatile memory cell' [patent_app_type] => 1 [patent_app_number] => 9/317976 [patent_app_country] => US [patent_app_date] => 1999-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 34 [patent_figures_cnt] => 49 [patent_no_of_words] => 19316 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 30 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/078/06078519.pdf [firstpage_image] =>[orig_patent_app_number] => 317976 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/317976
Semiconductor device, data processing system and a method for changing threshold of a non-volatile memory cell May 24, 1999 Issued
Array ( [id] => 4412641 [patent_doc_number] => 06232794 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-15 [patent_title] => 'Electronic circuit with automatic signal conversion' [patent_app_type] => 1 [patent_app_number] => 9/316470 [patent_app_country] => US [patent_app_date] => 1999-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5836 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/232/06232794.pdf [firstpage_image] =>[orig_patent_app_number] => 316470 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/316470
Electronic circuit with automatic signal conversion May 20, 1999 Issued
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