Search

David Lam

Examiner (ID: 14034, Phone: (571)272-1782 , Office: P/2825 )

Most Active Art Unit
2827
Art Unit(s)
2825, 2827, 2818
Total Applications
2102
Issued Applications
2016
Pending Applications
28
Abandoned Applications
60

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4097020 [patent_doc_number] => 06026039 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-15 [patent_title] => 'Parallel test circuit for semiconductor memory' [patent_app_type] => 1 [patent_app_number] => 9/215576 [patent_app_country] => US [patent_app_date] => 1998-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2005 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/026/06026039.pdf [firstpage_image] =>[orig_patent_app_number] => 215576 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/215576
Parallel test circuit for semiconductor memory Dec 16, 1998 Issued
Array ( [id] => 4217086 [patent_doc_number] => 06078543 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-20 [patent_title] => 'Refresh scheme for redundant word lines' [patent_app_type] => 1 [patent_app_number] => 9/209178 [patent_app_country] => US [patent_app_date] => 1998-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 3743 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/078/06078543.pdf [firstpage_image] =>[orig_patent_app_number] => 209178 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/209178
Refresh scheme for redundant word lines Dec 9, 1998 Issued
Array ( [id] => 3953677 [patent_doc_number] => 05973992 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-26 [patent_title] => 'Tracking signals' [patent_app_type] => 1 [patent_app_number] => 9/207304 [patent_app_country] => US [patent_app_date] => 1998-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3306 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/973/05973992.pdf [firstpage_image] =>[orig_patent_app_number] => 207304 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/207304
Tracking signals Dec 7, 1998 Issued
Array ( [id] => 4131149 [patent_doc_number] => 06072720 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-06 [patent_title] => 'Nonvolatile reprogrammable interconnect cell with programmable buried bitline' [patent_app_type] => 1 [patent_app_number] => 9/205876 [patent_app_country] => US [patent_app_date] => 1998-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 16 [patent_no_of_words] => 2768 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 220 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/072/06072720.pdf [firstpage_image] =>[orig_patent_app_number] => 205876 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/205876
Nonvolatile reprogrammable interconnect cell with programmable buried bitline Dec 3, 1998 Issued
Array ( [id] => 4127027 [patent_doc_number] => 06046952 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-04-04 [patent_title] => 'Method and apparatus for optimizing memory performance with opportunistic refreshing' [patent_app_type] => 1 [patent_app_number] => 9/205978 [patent_app_country] => US [patent_app_date] => 1998-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5551 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/046/06046952.pdf [firstpage_image] =>[orig_patent_app_number] => 205978 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/205978
Method and apparatus for optimizing memory performance with opportunistic refreshing Dec 3, 1998 Issued
Array ( [id] => 4261763 [patent_doc_number] => 06137728 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-24 [patent_title] => 'Nonvolatile reprogrammable interconnect cell with programmable buried source/drain in sense transistor' [patent_app_type] => 1 [patent_app_number] => 9/205678 [patent_app_country] => US [patent_app_date] => 1998-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 2512 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 223 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/137/06137728.pdf [firstpage_image] =>[orig_patent_app_number] => 205678 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/205678
Nonvolatile reprogrammable interconnect cell with programmable buried source/drain in sense transistor Dec 3, 1998 Issued
Array ( [id] => 4250359 [patent_doc_number] => 06081444 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-27 [patent_title] => 'Static memory adopting layout that enables minimization of cell area' [patent_app_type] => 1 [patent_app_number] => 9/204278 [patent_app_country] => US [patent_app_date] => 1998-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 2961 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/081/06081444.pdf [firstpage_image] =>[orig_patent_app_number] => 204278 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/204278
Static memory adopting layout that enables minimization of cell area Dec 2, 1998 Issued
Array ( [id] => 4155332 [patent_doc_number] => 06031774 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-29 [patent_title] => 'Internal power supply voltage generating ciruit and the method for controlling thereof' [patent_app_type] => 1 [patent_app_number] => 9/199166 [patent_app_country] => US [patent_app_date] => 1998-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3024 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/031/06031774.pdf [firstpage_image] =>[orig_patent_app_number] => 199166 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/199166
Internal power supply voltage generating ciruit and the method for controlling thereof Nov 24, 1998 Issued
Array ( [id] => 4197638 [patent_doc_number] => 06151246 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-21 [patent_title] => 'Multi-bit-per-cell flash EEPROM memory with refresh' [patent_app_type] => 1 [patent_app_number] => 9/200220 [patent_app_country] => US [patent_app_date] => 1998-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 6899 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/151/06151246.pdf [firstpage_image] =>[orig_patent_app_number] => 200220 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/200220
Multi-bit-per-cell flash EEPROM memory with refresh Nov 24, 1998 Issued
Array ( [id] => 4144709 [patent_doc_number] => 06034920 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-07 [patent_title] => 'Semiconductor memory device having a back gate voltage controlled delay circuit' [patent_app_type] => 1 [patent_app_number] => 9/198816 [patent_app_country] => US [patent_app_date] => 1998-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 16 [patent_no_of_words] => 3867 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/034/06034920.pdf [firstpage_image] =>[orig_patent_app_number] => 198816 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/198816
Semiconductor memory device having a back gate voltage controlled delay circuit Nov 23, 1998 Issued
Array ( [id] => 6126556 [patent_doc_number] => 20020075743 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-06-20 [patent_title] => 'ANTIFUSE ADDRESS DETECTING CIRCUIT PROGRAMMABLE BY APPLYING A HIGH VOLTAGE AND SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE PROVIDED WITH THE SAME' [patent_app_type] => new [patent_app_number] => 09/197566 [patent_app_country] => US [patent_app_date] => 1998-11-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 12333 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0075/20020075743.pdf [firstpage_image] =>[orig_patent_app_number] => 09197566 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/197566
Antifuse address detecting circuit programmable by applying a high voltage and semiconductor integrated circuit device provided with the same Nov 22, 1998 Issued
Array ( [id] => 4197442 [patent_doc_number] => 06094396 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-25 [patent_title] => 'Memory array architecture for multi-data rate operation' [patent_app_type] => 1 [patent_app_number] => 9/195269 [patent_app_country] => US [patent_app_date] => 1998-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 4338 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/094/06094396.pdf [firstpage_image] =>[orig_patent_app_number] => 195269 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/195269
Memory array architecture for multi-data rate operation Nov 17, 1998 Issued
Array ( [id] => 4251769 [patent_doc_number] => 06091641 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-18 [patent_title] => 'Non-volatile memory device and method for the programming of the same' [patent_app_type] => 1 [patent_app_number] => 9/195276 [patent_app_country] => US [patent_app_date] => 1998-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 1882 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/091/06091641.pdf [firstpage_image] =>[orig_patent_app_number] => 195276 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/195276
Non-volatile memory device and method for the programming of the same Nov 17, 1998 Issued
Array ( [id] => 4153192 [patent_doc_number] => 06061292 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-09 [patent_title] => 'Method and circuit for triggering column select line for write operations' [patent_app_type] => 1 [patent_app_number] => 9/195268 [patent_app_country] => US [patent_app_date] => 1998-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 3214 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/061/06061292.pdf [firstpage_image] =>[orig_patent_app_number] => 195268 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/195268
Method and circuit for triggering column select line for write operations Nov 17, 1998 Issued
Array ( [id] => 4393634 [patent_doc_number] => 06295220 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-25 [patent_title] => 'Memory bar and related circuits and methods' [patent_app_type] => 1 [patent_app_number] => 9/185276 [patent_app_country] => US [patent_app_date] => 1998-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 15 [patent_no_of_words] => 1659 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/295/06295220.pdf [firstpage_image] =>[orig_patent_app_number] => 185276 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/185276
Memory bar and related circuits and methods Nov 2, 1998 Issued
Array ( [id] => 3957333 [patent_doc_number] => 05982680 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-09 [patent_title] => 'Semiconductor memory' [patent_app_type] => 1 [patent_app_number] => 9/181976 [patent_app_country] => US [patent_app_date] => 1998-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 38 [patent_no_of_words] => 12456 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/982/05982680.pdf [firstpage_image] =>[orig_patent_app_number] => 181976 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/181976
Semiconductor memory Oct 28, 1998 Issued
Array ( [id] => 3960446 [patent_doc_number] => 05991211 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-23 [patent_title] => 'Semiconductor memory device with redundancy control circuits' [patent_app_type] => 1 [patent_app_number] => 9/181977 [patent_app_country] => US [patent_app_date] => 1998-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 20 [patent_no_of_words] => 9053 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 43 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/991/05991211.pdf [firstpage_image] =>[orig_patent_app_number] => 181977 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/181977
Semiconductor memory device with redundancy control circuits Oct 28, 1998 Issued
Array ( [id] => 4170416 [patent_doc_number] => 06104660 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-15 [patent_title] => 'Battery module and battery managing system' [patent_app_type] => 1 [patent_app_number] => 9/181817 [patent_app_country] => US [patent_app_date] => 1998-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 6305 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/104/06104660.pdf [firstpage_image] =>[orig_patent_app_number] => 181817 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/181817
Battery module and battery managing system Oct 28, 1998 Issued
Array ( [id] => 4153072 [patent_doc_number] => 06061284 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-09 [patent_title] => 'Core test control' [patent_app_type] => 1 [patent_app_number] => 9/179168 [patent_app_country] => US [patent_app_date] => 1998-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 2412 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/061/06061284.pdf [firstpage_image] =>[orig_patent_app_number] => 179168 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/179168
Core test control Oct 25, 1998 Issued
Array ( [id] => 4191978 [patent_doc_number] => 06038176 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-14 [patent_title] => 'Presettable semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 9/178872 [patent_app_country] => US [patent_app_date] => 1998-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 15 [patent_no_of_words] => 6589 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/038/06038176.pdf [firstpage_image] =>[orig_patent_app_number] => 178872 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/178872
Presettable semiconductor memory device Oct 25, 1998 Issued
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